[Intel-gfx] [PATCH 06/10] drm/i915: Enable DSI PLL for both DSI0 and DSI1 in case of dual link

[Jani Nikula]

On Thu, 04 Dec 2014, Gaurav K Singh <gaurav.k.singh at intel.com> wrote:
> For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be enabled.
>
> v2: Address review comments by Jani
>     - Added wait time for PLL to be locked.
>
> v3: separate patch created for cck read for checking PLL to be locked
>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh at intel.com>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index fa7a6ca..636d72f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  
>  	dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL;
>  
> +	if (intel_dsi->dual_link)
> +		dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL;
> +
>  	DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n",
>  		      dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl);
>  
> -- 
> 1.7.9.5
>
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-- 
Jani Nikula, Intel Open Source Technology Center