[Intel-gfx] [PATCH] drm/i915/bdw: Fix the write setting up the WIZ hashing mode

[Damien Lespiau]

On Mon, Dec 08, 2014 at 02:33:57PM +0200, Jani Nikula wrote:
> >  #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
> >  #define _MASKED_BIT_DISABLE(a) ((a) << 16)
> > +#define _MASKED_FIELD(value, mask) (((mask) << 16) | (value))
> 
> Obligatory bikeshed, wouldn't you say _MASKED_BIT_{ENABLE,DISABLE} are
> special cases of _MASKED_FIELD...? ;)

That's because we're not just enabling or disabling bits here but
setting a multi-bits value.

  _MASKED_FIELD(2 << 4, 0x3 << 4);

-- 
Damien