[Intel-gfx] [PATCH 8/3] drm/i915: WARN in case we're enabling the pipe and it's enabled

[Damien Lespiau]

On Fri, Jan 17, 2014 at 01:51:13PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> ... and QUIRK_PIPEA_FORCE is not present.
> 
> I initially thought that case was impossible and just added a WARN on
> it, but then I was told this case is possible due to
> QUIRK_PIPEA_FORCE. So let's add a WARN that serves two purposes:
>   - tell us in case we have done something wrong;
>   - document the only case where we expect this.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9f356f9..e2df886 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1791,8 +1791,11 @@ static void intel_enable_pipe(struct intel_crtc *crtc)
>  
>  	reg = PIPECONF(cpu_transcoder);
>  	val = I915_READ(reg);
> -	if (val & PIPECONF_ENABLE)
> +	if (val & PIPECONF_ENABLE) {
> +		WARN_ON(!(pipe == PIPE_A &&
> +			  dev_priv->quirks & QUIRK_PIPEA_FORCE));
>  		return;
> +	}
>  
>  	I915_WRITE(reg, val | PIPECONF_ENABLE);
>  	POSTING_READ(reg);
> -- 
> 1.8.4.2
> 
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