[Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail

[Purushothaman, Vijay A]

> -----Original Message-----
> From: Deak, Imre
> Sent: Wednesday, February 12, 2014 10:57 PM
> To: Purushothaman, Vijay A
> Cc: Intel Graphics; Daniel Vetter
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix correct FIFO size for Baytrail
> 
> On Wed, 2014-02-12 at 19:24 +0200, Imre Deak wrote:
> > On Fri, 2014-02-07 at 19:58 +0100, Daniel Vetter wrote:
> > > On Fri, Feb 07, 2014 at 05:58:16PM +0200, Ville Syrjälä wrote:
> > > > On Fri, Feb 07, 2014 at 08:43:12PM +0530, Vijay Purushothaman wrote:
> > > > > B-spec says the FIFO total size is 512. So fix this to 512.
> > > > >
> > > > > Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/i915_reg.h |    2 +-
> > > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> > > > > index cc3ea04..fb73031 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > > @@ -3395,7 +3395,7 @@
> > > > >  #define I915_FIFO_LINE_SIZE	64
> > > > >  #define I830_FIFO_LINE_SIZE	32
> > > > >
> > > > > -#define VALLEYVIEW_FIFO_SIZE	255
> > > > > +#define VALLEYVIEW_FIFO_SIZE	511
> > > > >  #define G4X_FIFO_SIZE		127
> > > > >  #define I965_FIFO_SIZE		512
> > > > >  #define I945_FIFO_SIZE		127
> > > >
> > > > Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > >
> > > Queued for -next, thanks for the patch.
> > > -Daniel
> >
> > This breaks DP on my BYT, I get bad flicker with it. Reverting only this
> > one fixes the issue.
> 
> Adding Vijay.
> 
> --Imre

Oops.. Sorry.. I didn’t expect this to break anything.. Please revert this patch.

I will test this change along with other drain latency & PFI credit patches and resubmit this again...

Thanks,
Vijay