[Intel-gfx] [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only

Daniel Vetter daniel at ffwll.ch
Mon Jan 27 08:28:58 CET 2014


On Sun, Jan 26, 2014 at 08:43:53PM +0000, Runyan, Arthur J wrote:
> 
> 
> >-----Original Message-----
> >From: Daniel Vetter [mailto:daniel.vetter at ffwll.ch]
> >Sent: Wednesday, January 22, 2014 2:40 PM
> >To: Intel Graphics Development
> >Cc: Daniel Vetter; Chris Wilson; Runyan, Arthur J; Dave Airlie
> >Subject: [PATCH] drm/i915: GEN7_MSG_CONTROL is ivb-only
> >
> >At least I couldn't find it in the Haswell Bspec any more and we've
> >tried to test-boot a Haswell machine with num_pipes forced to 0 (i.e.
> >hit the PCH_NOP path) and the unclaimed register logic complained.
> >
> >So restrict this dance to just ivb platforms.
> >
> >v2: Art pointed out that the bits simply moved on hsw+
> >
> >v3: Buy code terseneness with a notch of sublety as suggested by
> >Chris.
> >
> >v4: Frob the right bit, spotted by Art.
> >
> >Cc: Chris Wilson <chris at chris-wilson.co.uk>
> >Cc: Arthur Ranyan <arthur.j.runyan at intel.com>
> >Cc: Dave Airlie <airlied at gmail.com>
> >Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> 
> Reviewed-by: Art Runyan <arthur.j.runyan at intel.com>

Queued for -next, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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