[Intel-gfx] [PATCH] drm/i915/chv: WaDisablePwrmtrEvent:chv on CHV only

[Damien Lespiau]

On Mon, Jun 09, 2014 at 10:06:49AM -0700, Tom.O'Rourke at intel.com wrote:
> From: Tom O'Rourke <Tom.O'Rourke at intel.com>
> 
> In gen8_enable_rps, don't write CHV registers unless IS_CHERRYVIEW.
> 
> Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>

A lovely catch.

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/intel_pm.c |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d9c5918..3d3e402 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3522,8 +3522,10 @@ static void gen8_enable_rps(struct drm_device *dev)
>  	I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
>  
>  	/* WaDisablePwrmtrEvent:chv (pre-production hw) */
> -	I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
> -	I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
> +	if (IS_CHERRYVIEW(dev)) {
> +		I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
> +		I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
> +	}
>  
>  	/* 5: Enable RPS */
>  	I915_WRITE(GEN6_RP_CONTROL,
> -- 
> 1.7.9.5
> 
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