[Intel-gfx] [PATCH] drm/i915: Add some L3 registers to the parser whitelist

[Daniel Vetter]

On Tue, Jun 17, 2014 at 02:10:34PM -0700, bradley.d.volkin at intel.com wrote:
> From: Brad Volkin <bradley.d.volkin at intel.com>
> 
> Beignet needs these in order to program the L3 cache config for
> OpenCL workloads, particularly when using SLM.
> 
> Signed-off-by: Brad Volkin <bradley.d.volkin at intel.com>

Queued for -next, thanks for the patch.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_cmd_parser.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h        | 2 ++
>  2 files changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
> index 9d79543..dea99d9 100644
> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c
> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
> @@ -426,6 +426,9 @@ static const u32 gen7_render_regs[] = {
>  	GEN7_SO_WRITE_OFFSET(1),
>  	GEN7_SO_WRITE_OFFSET(2),
>  	GEN7_SO_WRITE_OFFSET(3),
> +	GEN7_L3SQCREG1,
> +	GEN7_L3CNTLREG2,
> +	GEN7_L3CNTLREG3,
>  };
>  
>  static const u32 gen7_blt_regs[] = {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e1fb0f2..3488567 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4670,6 +4670,8 @@ enum punit_power_well {
>  #define GEN7_L3CNTLREG1				0xB01C
>  #define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C
>  #define  GEN7_L3AGDIS				(1<<19)
> +#define GEN7_L3CNTLREG2				0xB020
> +#define GEN7_L3CNTLREG3				0xB024
>  
>  #define GEN7_L3_CHICKEN_MODE_REGISTER		0xB030
>  #define  GEN7_WA_L3_CHICKEN_MODE				0x20000000
> -- 
> 1.8.3.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch