[Intel-gfx] [PATCH 12/12] drm/i915/bdw: Restore PPAT on thaw

[Ben Widawsky]

From: Ben Widawsky <benjamin.widawsky at intel.com>

Apparently it is wiped out from under us, and we get some really fun
caching artifacts upon resume (it seems to be WB for all types by
default).

Reported-by: James Ausmus <james.ausmus at intel.com>
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Tested-by: James Ausmus <james.ausmus at intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76113
Tested-by: Timo Aaltonen <timo.aaltonen at canonical.com>
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
[BDW 3.14 backport]
Cc: stable at vger.kernel.org
Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

Conflicts:
	drivers/gpu/drm/i915/i915_gem_gtt.c
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 8cc9398..268e0d3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -28,6 +28,8 @@
 #include "i915_trace.h"
 #include "intel_drv.h"
 
+static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv);
+
 #define GEN6_PPGTT_PD_ENTRIES 512
 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
 typedef uint64_t gen8_gtt_pte_t;
@@ -865,6 +867,9 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
 		i915_gem_gtt_bind_object(obj, obj->cache_level);
 	}
 
+	if (INTEL_INFO(dev)->gen >= 8)
+		gen8_setup_private_ppat(dev_priv);
+
 	i915_gem_chipset_flush(dev);
 }
 
-- 
1.9.1