[Intel-gfx] [PATCH 06/10] drm/i915: VLV/CHV PSR Software timer mode control

[R, Durgadoss]

>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces at lists.freedesktop.org] On Behalf Of
>Rodrigo Vivi
>Sent: Wednesday, October 29, 2014 12:16 AM
>To: intel-gfx at lists.freedesktop.org
>Cc: Vivi, Rodrigo
>Subject: [Intel-gfx] [PATCH 06/10] drm/i915: VLV/CHV PSR Software timer mode
>control
>
>This patch introduces exit/activate functions for PSR
>on VLV+. Since on VLV+ HW cannot track frame updates and force PSR
>exit let's use fully SW tracking available.
>
>Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>---
> drivers/gpu/drm/i915/intel_dp.c | 94
>+++++++++++++++++++++++++++++++++++------
> 1 file changed, 81 insertions(+), 13 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 813537a..6829ecb 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -2271,6 +2271,27 @@ static void vlv_edp_psr_enable_source(struct intel_dp
>*intel_dp)
> }
>
> /**
>+ * vlv_edp_psr_activate - Activate PSR on VLV
>+ * @intel_dp: DP struct
>+ *
>+ * This function do the transition from PSR_state 1 to PSR_state 2 that is
>+ * PSR transition to active - static frame transmission.
>+ * Then Hardware is responsible for the transition to PSR_state 3 that is
>+ * PSR active - no Remote Frame Buffer (RFB) update.
>+ */
>+static void vlv_edp_psr_activate(struct intel_dp *intel_dp)
>+{
>+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>+	struct drm_device *dev = dig_port->base.base.dev;
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct drm_crtc *crtc = dig_port->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+
>+	I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
>+		   VLV_EDP_PSR_ACTIVE_ENTRY);
>+}
>+
>+/**
>  * hsw_edp_psr_enable_source - Enable PSR on Source.
>  * @intel_dp: DP struct
>  *
>@@ -2370,12 +2391,15 @@ static void intel_edp_psr_activate(struct intel_dp
>*intel_dp)
> 	WARN_ON(dev_priv->psr.active);
> 	lockdep_assert_held(&dev_priv->psr.lock);
>
>-	/* Enable/Re-enable PSR on the host
>-	 * On HSW/BDW after we enable PSR on source it will activate it
>-	 * as soon as it match configure idle_frame count. So
>-	 * we just actually enable it here on activation time.
>-	 */
>-	hsw_edp_psr_enable_source(intel_dp);
>+	/* Enable/Re-enable PSR on the host */
>+	if (HAS_DDI(dev))
>+		/* On HSW/BDW after we enable PSR on source it will activate it
>+		 * as soon as it match configure idle_frame count. So
>+		 * we just actually enable it here on activation time.
>+		 */
>+		hsw_edp_psr_enable_source(intel_dp);
>+	else
>+		vlv_edp_psr_activate(intel_dp);
>
> 	dev_priv->psr.active = true;
> }
>@@ -2514,18 +2538,30 @@ static void intel_edp_psr_work(struct work_struct
>*work)
> 	struct drm_i915_private *dev_priv =
> 		container_of(work, typeof(*dev_priv), psr.work.work);
> 	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+	struct drm_crtc *crtc = dp_to_dig_port(
>+		dev_priv->psr.enabled)->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>
> 	/* We have to make sure PSR is ready for re-enable
> 	 * otherwise it keeps disabled until next full enable/disable cycle.
> 	 * PSR might take some time to get fully disabled
> 	 * and be ready for re-enable.
> 	 */
>-	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>-		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>-		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>-		return;
>+	if (HAS_DDI(dev_priv->dev)) {
>+		if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
>+			      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
>+			DRM_ERROR("Timed out waiting for PSR Idle for re-
>enable\n");
>+			return;
>+		}
>+	} else {
>+		if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
>+			      VLV_EDP_PSR_IN_TRANS) == 0, 250)) {
>+			DRM_ERROR("Timed out waiting for PSR Idle for re-
>enable\n");
>+			return;
>+		}
> 	}
>
>+
> 	mutex_lock(&dev_priv->psr.lock);
> 	intel_dp = dev_priv->psr.enabled;
>
>@@ -2555,17 +2591,49 @@ unlock:
> static void intel_edp_psr_exit(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_dp *intel_dp = dev_priv->psr.enabled;
>+	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
>+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>+	u32 val;
>
>-	if (dev_priv->psr.active) {
>-		u32 val = I915_READ(EDP_PSR_CTL(dev));
>+	if (!dev_priv->psr.active)
>+		return;
>+
>+	if (HAS_DDI(dev)) {
>+		val = I915_READ(EDP_PSR_CTL(dev));
>
> 		WARN_ON(!(val & EDP_PSR_ENABLE));
>
> 		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
>+	} else {
>+		val = I915_READ(VLV_PSRCTL(pipe));
>
>-		dev_priv->psr.active = false;
>+		/* Here we do the transition from PSR_state 3 to PSR_state 4
>+		 * that is PSR active - Single frame update
>+		 */
>+		val |= VLV_EDP_PSR_SINGLE_FRAME_UPDATE;
>+		I915_WRITE(VLV_PSRCTL(pipe), val);

Do we really need this step ?
i.e The state machine can go to state 5 from state 3 directly.
So, this should not be really needed. Can we double check once ?

>+
>+		/* Now we are able to proceed to PSR_state 5 that is PSR exit
>+		 * then Hardware is responsible to transition back to
>+		 * PSR_state 1 that is PSR inactive. Same state after
>+		 * vlv_edp_psr_enable_source.
>+		 */
>+		val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
>+		I915_WRITE(VLV_PSRCTL(pipe), val);
>+
>+		/* Send AUX wake up - Spec says after transitioning to PSR
>+		 * active we have to send AUX wake up by writing 01h in DPCD
>+		 * 600h of sink device.
>+		 * XXX: This might slow down the transition, but without this
>+		 * HW doesn't complete the transition to PSR_state 1 and we
>+		 * never get the screen updated.
>+		 */
>+		drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
>+				   DP_SET_POWER_D0);

Any specific reason for not using 'intel_sink_dpms_on(dp, MODE_ON) ?

Thanks,
Durga

> 	}
>
>+	dev_priv->psr.active = false;
> }
>
> void intel_edp_psr_invalidate(struct drm_device *dev,
>--
>1.9.3
>
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