[Intel-gfx] [PATCH 1/4] drm/i915: HSW/BDW PSR Set idle_frames = VBT + 1

[Daniel Vetter]

On Fri, Nov 07, 2014 at 03:55:15PM -0800, Rodrigo Vivi wrote:
> Let's use VBT + 1 now we parse it.

This patch completely lacks the justification for why we need this. Please
add a short summary of our previous discussion with Art.

> 
> v2: fix subject and consider that idle_frame = 2 is another fix.
> 
> Cc: Arthur Runyan <arthur.j.runyan at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 20beb59..41df221 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2174,7 +2174,12 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
>  	struct drm_device *dev = dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	uint32_t max_sleep_time = 0x1f;
> -	uint32_t idle_frames = 2; /* 2 is the minimum allowed */

Doesn't apply because the v1 series seems to be missing. I tried to fix
that but then it wouldn't compile because I'm missing the vbt patch.

Please always send the full patch series or mention unmerged depencies in
the cover letter.
-Daniel
> +	/* Lately it was identified that depending on panel idle frame count
> +	 * calculated at HW can be off by 1. So let's use what came
> +	 * from VBT + 1 and at minimum 2 to stay on the safest side.
> +	 */
> +	uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
> +			       dev_priv->vbt.psr.idle_frames + 1 : 2;
>  	uint32_t val = 0x0;
>  	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
>  	bool only_standby = false;
> -- 
> 1.9.3
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch