[Intel-gfx] [PATCH 8/8] drm/i915: Wait thread status on gen8+ fw sequence

[Ville Syrjälä]

On Wed, Nov 12, 2014 at 10:28:10AM +0100, Daniel Vetter wrote:
> On Tue, Nov 11, 2014 at 07:12:29PM +0200, Ville Syrjälä wrote:
> > On Mon, Nov 10, 2014 at 04:52:50AM -0800, Rodrigo Vivi wrote:
> > > From: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> > > 
> > > As per latest pm guide, we need to do this also on
> > > past hsw.
> > 
> > Yep, matches the doc.
> > 
> > Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Queued for -next, thanks for the patch.
> > 
> > BTW I wonder why we also wait for the [18:16] bits to clear on HSW? I don't
> > see such a thing documented in the HSW PM guide I have here. Maybe we can
> > just drop the HSW special case?
> 
> Iirc (commit message is silent unfortunately) this is for the GT3. And
> since they're 0 on other hsw we've opted for a tricky silent gt3 enabling
> by claiming this is for all of hsw. At least that's the story I remember.
> 
> No idea whether bdw gt3 would need this, too. Might be good to
> double-check.

The docs claim these are the same old thread wish result bits ever since
snb.

I just tried intel_reg_read on hsw gt2 and gt3 and both give identical
results to ivb. So my hunch is that we can just drop the hsw special
case.

-- 
Ville Syrjälä
Intel OTC