[Intel-gfx] [PATCH 00/10] SKL stage 1 part 3

[Damien Lespiau]

Another series of reviewed patches. This time SKL clocks minus DPLL0 (eDP) and
a extra small patch to not apply the HSW/BDW eDP link training W/A.

-- 
Damien

Damien Lespiau (1):
  drm/i915/skl: Provide skl-specific pll hw state cross-checking

Satheeshakrishna M (8):
  drm/i915/skl: Register definitions for SKL Clocks
  drm/i915/skl: Structure/enum definitions for SKL clocks
  drm/i915/skl: CD clock back calculation for SKL
  drm/i915/skl: Determine enabled PLL and its linkrate/pixel clock
  drm/i915/skl: Query DPLL attached to port on SKL
  drm/i915/skl: Define shared DPLLs for Skylake
  drm/i915/skl: Adjust the port PLL selection code
  drm/i915/skl: Implementation of SKL DPLL programming

Vandana Kannan (1):
  drm/i915/skl: Apply eDP WA only for gen < 9

 drivers/gpu/drm/i915/i915_drv.h      |  23 +-
 drivers/gpu/drm/i915/i915_reg.h      |  77 +++++
 drivers/gpu/drm/i915/intel_ddi.c     | 576 +++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_display.c |  32 +-
 drivers/gpu/drm/i915/intel_drv.h     |   5 +-
 5 files changed, 691 insertions(+), 22 deletions(-)

-- 
1.8.3.1