[Intel-gfx] [PATCH 14/14] drm/i915: Reinit display irqs and hpd from chv pipe-a power well

[Daniel Vetter]

On Fri, Nov 14, 2014 at 08:45:05PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 14, 2014 at 03:49:25PM -0200, Paulo Zanoni wrote:
> > 2014-10-30 15:43 GMT-02:00  <ville.syrjala at linux.intel.com>:
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > >
> > > On chv the pipe-a power well is the new disp2d well, and it kills pretty
> > > much everything in the display block. So we need to do the the same
> > > dance that vlv does wrt. display irqs and hpd when the power well goes
> > > up or down.
> > 
> > I don't have the docs for this, so I have to ask: does it kill *all*
> > the interrupt bits (like VLV), or does it kill only the pipe A
> > interrupt bits (like BDW on pipes B/C)?
> > 
> > If it kills everything: Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> Yeah, everything goes even though it's called the "pipe A" power well.
> I think the plan was to have per-pipe wells, but then someone decided that
> it's not worth it. For some reason they still hooked it up to the pipe A
> power well bits instead of doing the more sensible thing and reusing the
> same bits that VLV used for this stuff.

Ok, I've merged the remaining patches from this series, thanks.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch