[Intel-gfx] [PATCH 00/18] drm/i915: All sorts of cdclk stuff

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

My main motivation here was to get dev_priv->max_cdclk into place on
all platforms so that we can start to use it to validate modes and
whatnot. This series doesn't actually add any new checks like that
apart from the BDW IPS case, and converting over whatever checks we
already had.

The other thing I managed to do is add support for cdclk dynamic
frequency scaling on HSW/BDW, and I also fixed it for CHV.

The HSW stuff we may want to drop actually since I was told it's not
validated, and it doesn't scale the voltage in any case so the benefits
may not be worth it. I did try it out on my HSW here and it seemed to
work just fine. In any case I figured I'll include the patch anyway.

As usual, the CHV case is again a major documentation snafu. Let's
just say I made it work despite the documentation. The 400MHz case
doesn't seem to work actually, or rather the Punit seems to reject
any request above 320MHz. Also the 200MHz case seems as busted as on
VLV. I just get an immediate underrun and a black screen, even though
the pixel clock is definitely below the 90% of cdclk limit.

I pushed the lot (+ a hack to force a higher cdclk via a modparam)
here:
git://gitorious.org/vsyrjala/linux.git cdclk_7

Ville Syrjälä (18):
  drm/i915: Return more precise cdclk for gen2/3
  drm/i915: Fix i855_get_display_clock_speed()
  drm/i915: Fix 852GM/GMV cdclk
  drm/i915: Add cdclk extraction for g33, 965gm and g4x
  drm/i915: ILK cdclk seems to be 450MHz
  drm/i915: Assume 400 MHz cdclk for the rest of gen4-7
  drm/i915: Simplify ilk_get_aux_clock_divider()
  drm/i915: Convert the ddi cdclk code to .get_display_clock_speed()
  drm/i915: Warn when cdclk for the platforms is not known
  drm/i915: Cache the current cdclk frequency in dev_priv
  drm/i915: Use cached cdclk value
  drm/i915: Unify ilk and hsw .get_aux_clock_divider()
  drm/i915: Store max cdclk value in dev_priv
  drm/i915: Don't enable IPS when pixel rate exceeds 95% of cdclk
  drm/i915: Fix chv cdclk support
  drm/i915: HSW cdclk change support
  drm/i915: Add IS_BDW_ULX()
  drm/i915: BDW cdclk change support

 drivers/gpu/drm/i915/i915_drv.h         |   5 +-
 drivers/gpu/drm/i915/i915_reg.h         |  18 +-
 drivers/gpu/drm/i915/intel_ddi.c        | 101 +----
 drivers/gpu/drm/i915/intel_display.c    | 697 +++++++++++++++++++++++++++++---
 drivers/gpu/drm/i915/intel_dp.c         |  26 +-
 drivers/gpu/drm/i915/intel_drv.h        |   2 +-
 drivers/gpu/drm/i915/intel_pm.c         |  18 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |   2 +-
 8 files changed, 672 insertions(+), 197 deletions(-)

-- 
2.0.4