[Intel-gfx] [PATCH 2/4] drm/i915/skl: Set the eDP link rate on DPLL0

Daniel Vetter daniel at ffwll.ch
Mon Nov 17 19:24:57 CET 2014


On Fri, Nov 14, 2014 at 05:24:33PM +0000, Damien Lespiau wrote:
> On SKL DPLL0 is used to derive CDCLK but can also be used to drive an
> eDP port (as long as we don't want SSC). DPLL0 is special enough to not
> be handled by the shared DPLL framework (drives CDCLK, not supposed to
> enable the HDMI mode), So we need to compute the configuration
> separately from the other DPLLs.
> 
> Note that we don't need to reprogram DPLL0 (which would mean bringing
> down CDCLK) to support the various eDP 1.3 link rates as they all share
> the same VCO (8100).
> 
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 20 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dp.c  | 31 ++++++++++++++++++++++++++++++-
>  2 files changed, 50 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ca33ee9..596bdc1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1484,6 +1484,25 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
>  		uint32_t dpll = crtc->config.ddi_pll_sel;
>  		uint32_t val;
>  
> +		/*
> +		 * DPLL0 is used for eDP and is the only "private" DPLL (as
> +		 * opposed to shared) on SKL
> +		 */
> +		if (type == INTEL_OUTPUT_EDP) {

Are you sure you really want to check for edp here and not for something
more specific like port A? Same with the is_edp check below.

In the past we've had piles of fun with code that checked for is_edp, but
which should have checked for port A or something similar - on desktop
platforms (at least in all chips thus far, dunno about skl) edp ends up on
port D.

Oh and someone bored might want to replace the pile of type == DP || type
== EDP checks in intel_ddi.c with config->has_dp_encoder.

I'll hold off on merging this for now just out of curiosity ;-)
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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