[Intel-gfx] [PATCH 79/89] drm/i915/skl: Read back the DDB allocation hw state

[Ville Syrjälä]

On Thu, Sep 04, 2014 at 12:27:45PM +0100, Damien Lespiau wrote:
> This logically belongs to the WM state, so do it there.
> 
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d378879..8d24a4d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3020,6 +3020,32 @@ static unsigned int skl_cursor_allocation(struct intel_wm_config *config)
>  	return 8;
>  }
>  
> +static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
> +{
> +	entry->start = reg & 0x3ff;
> +	entry->end = (reg >> 16) & 0x3ff;

Would need a rebase in case the HW register is really inclusive and we
make skl_ddb_entry.end exclusive.

Apart from that 
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> +}
> +
> +static void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> +				 struct skl_ddb_allocation *ddb /* out */)
> +{
> +	struct drm_device *dev = dev_priv->dev;
> +	enum pipe pipe;
> +	int plane;
> +	u32 val;
> +
> +	for_each_pipe(dev_priv, pipe) {
> +		for_each_plane(pipe, plane) {
> +			val = I915_READ(PLANE_BUF_CFG(pipe, plane));
> +			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
> +						   val);
> +		}
> +
> +		val = I915_READ(CUR_BUF_CFG(pipe));
> +		skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
> +	}
> +}
> +
>  static unsigned int
>  skl_plane_relative_data_rate(struct intel_plane_wm_parameters *p)
>  {
> @@ -3810,8 +3836,11 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
>  
>  void skl_wm_get_hw_state(struct drm_device *dev)
>  {
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
>  	struct drm_crtc *crtc;
>  
> +	skl_ddb_get_hw_state(dev_priv, ddb);
>  	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
>  		skl_pipe_wm_get_hw_state(crtc);
>  }
> -- 
> 1.8.3.1
> 
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-- 
Ville Syrjälä
Intel OTC