[Intel-gfx] [PATCH v4 4/8] drm/i915/skl: Assert the requirements to enter or exit DC5.
Imre Deak
imre.deak at intel.com
Thu Apr 30 06:26:11 PDT 2015
On to, 2015-04-16 at 14:22 +0530, Animesh Manna wrote:
> From: Suketu Shah <suketu.j.shah at intel.com>
>
> Warn if the conditions to enter or exit DC5 are not satisfied such
> as support for runtime PM, state of power well, CSR loading etc.
>
> v2: Removed camelcase in functions and variables.
>
> v3: Do some minimal check to assert if CSR program is not loaded.
>
> v4:
> 1] Used an appropriate function lookup_power_well() to identify power well,
> instead of using a magic number which can change in future.
> 2] Split the conditions further in assert_can_enable_DC5() and added more checks.
> 3] Removed all WARNs from assert_can_disable_DC5 as they were unnecessary and added two
> new ones.
> 4] Changed variable names as updated in earlier patches.
>
> v5:
> 1] Change lookup_power_well function to take an int power well id.
> 2] Define a new intel_display_power_well_is_enabled helper function to check whether a
> particular power well is enabled.
> 3] Use CSR-related mutex in assert_csr_loaded function.
>
> v6: Remove use of dc5_enabled variable as it's no longer needed.
>
> v7:
> 1] Rebase to latest.
> 2] Move all DC5-related functions from intel_display.c to intel_runtime_pm.c.
>
> v8: After adding dmc ver 1.0 support rebased on top of nightly. (Animesh)
>
> v9: Modified below changes based on review comments from Imre.
> - Moved intel_display_power_well_is_enabled() to intel_runtime_pm.c.
> - Removed mutex lock from assert_csr_loaded(). (Animesh)
>
> Issue: VIZ-2819
> Signed-off-by: A.Sunil Kamath <sunil.kamath at intel.com>
> Signed-off-by: Suketu Shah <suketu.j.shah at intel.com>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> Signed-off-by: Animesh Manna <animesh.manna at intel.com>
Reviewed-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/intel_csr.c | 9 ++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 51 +++++++++++++++++++++++++++++----
> 3 files changed, 56 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
> index fe6789f..d58effe 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -410,3 +410,12 @@ void intel_csr_ucode_fini(struct drm_device *dev)
> intel_csr_load_status_set(dev_priv, FW_FAILED);
> kfree(dev_priv->csr.dmc_payload);
> }
> +
> +void assert_csr_loaded(struct drm_i915_private *dev_priv)
> +{
> + WARN((intel_csr_load_status_get(dev_priv) != FW_LOADED), "CSR is not loaded.\n");
> + WARN(!I915_READ(CSR_PROGRAM_BASE),
> + "CSR program storage start is NULL\n");
> + WARN(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
> + WARN(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
> +}
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 25d7956..2eb0169 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1069,6 +1069,7 @@ void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
> enum csr_state state);
> void intel_csr_load_program(struct drm_device *dev);
> void intel_csr_ucode_fini(struct drm_device *dev);
> +void assert_csr_loaded(struct drm_i915_private *dev_priv);
>
> /* intel_dp.c */
> void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 466ea69..da8c18d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -64,6 +64,9 @@
> i--) \
> if ((power_well)->domains & (domain_mask))
>
> +bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> + int power_well_id);
> +
> /*
> * We should only use the power well if we explicitly asked the hardware to
> * enable it, so check if it's enabled and also check if we've requested it to
> @@ -335,12 +338,39 @@ static void gen9_set_dc_state_debugmask_memory_up(
> }
> }
>
> -static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> +static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> {
> struct drm_device *dev = dev_priv->dev;
> + bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
> + SKL_DISP_PW_2);
> +
> + WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
> + WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
> + WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n");
> +
> + WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
> + "DC5 already programmed to be enabled.\n");
> + WARN(dev_priv->pm.suspended,
> + "DC5 cannot be enabled, if platform is runtime-suspended.\n");
> +
> + assert_csr_loaded(dev_priv);
> +}
> +
> +static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
> +{
> + bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
> + SKL_DISP_PW_2);
> +
> + WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n");
> + WARN(dev_priv->pm.suspended,
> + "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
> +}
> +
> +static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> +{
> uint32_t val;
>
> - WARN_ON(!IS_GEN9(dev));
> + assert_can_enable_dc5(dev_priv);
>
> DRM_DEBUG_KMS("Enabling DC5\n");
>
> @@ -355,10 +385,9 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>
> static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
> {
> - struct drm_device *dev = dev_priv->dev;
> uint32_t val;
>
> - WARN_ON(!IS_GEN9(dev));
> + assert_can_disable_dc5(dev_priv);
>
> DRM_DEBUG_KMS("Disabling DC5\n");
>
> @@ -1318,7 +1347,7 @@ static struct i915_power_well chv_power_wells[] = {
> };
>
> static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
> - enum punit_power_well power_well_id)
> + int power_well_id)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *power_well;
> @@ -1332,6 +1361,18 @@ static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_pr
> return NULL;
> }
>
> +bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
> + int power_well_id)
> +{
> + struct i915_power_well *power_well;
> + bool ret;
> +
> + power_well = lookup_power_well(dev_priv, power_well_id);
> + ret = power_well->ops->is_enabled(dev_priv, power_well);
> +
> + return ret;
> +}
> +
> static struct i915_power_well skl_power_wells[] = {
> {
> .name = "always-on",
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