[Intel-gfx] [RFC 1/8] drm/915/bxt: Adding DSC VBT parameter and PPS structures

[vikas.korjani at intel.com]

From: vkorjani <vikas.korjani at intel.com>

Adding pps structure as per VESA DSC v1.1 spec.
Adding "vbt_dsc_param" vbt structure to store DSC info
vbt_dsc_param and pps structures are made part of intel_vbt_data.

Signed-off-by: vkorjani <vikas.korjani at intel.com>
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h   |    2 +
 drivers/gpu/drm/i915/intel_bios.h |   73 +++++++++++++++++++++++++++++++++++++
 2 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e1a9b0f..78f293f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1492,6 +1492,8 @@ struct intel_vbt_data {
 	union child_device_config *child_dev;
 
 	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
+	struct vbt_dsc_param dsc_param;
+	struct vbt_dsc_capablity_param capab_param;
 };
 
 enum intel_ddb_partitioning {
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h
index af0b476..8bc7c87 100644
--- a/drivers/gpu/drm/i915/intel_bios.h
+++ b/drivers/gpu/drm/i915/intel_bios.h
@@ -778,6 +778,79 @@ int intel_parse_bios(struct drm_device *dev);
 #define MIPI_DSI_UNDEFINED_PANEL_ID	0
 #define MIPI_DSI_GENERIC_PANEL_ID	1
 
+struct vesa_dsc_rc_range_param {
+	u8 range_min_qp;
+	u8 range_max_qp;
+	u8 range_bpg_offset;
+};
+
+struct vesa_dsc_rc_param {
+	u16 model_size;
+	u8 rc_edge_factor;
+	u8 rc_quant_incr_limit0;
+	u8 rc_quant_incr_limit1;
+	u8 rc_tgt_offset_hi;
+	u8 rc_tgt_offset_lo;
+	u8 rc_buf_thresh[14];
+	struct vesa_dsc_rc_range_param rc_range[16];
+};
+
+struct vesa_dsc_pps_data {
+	u8 dsc_ver_major;
+	u8 dsc_ver_minor;
+	u8 pps_identifier;
+	u8 bit_per_comp;
+	u8 line_buf_depth;
+	u8 block_pred_enable;
+	u8 convert_rgb;
+	u8 enable_422;
+	u8 enable_vbr;
+	u16 bits_per_pixel;
+	u16 pic_width;
+	u16 pic_height;
+	u16 slice_width;
+	u16 slice_height;
+	u16 chunk_size;
+	u16 initial_xmit_delay;
+	u16 initial_dec_delay;
+	u8 initial_scale_value;
+	u16 scale_increment_interval;
+	u16 scale_decrement_interval;
+	u8 first_line_bpg_offset;
+	u16 nfl_bpg_offset;
+	u16 slice_bpg_offset;
+	u16 initial_offset;
+	u16 final_offset;
+	u8 flatness_min_qp;
+	u8 flatness_max_qp;
+	struct vesa_dsc_rc_param rc_param;
+};
+
+struct vbt_dsc_capablity_param {
+	u8 block_prediction_allowed;
+	u8 disp_bpc;
+	u8 line_buf_bit_depth;
+	u16 picture_height;
+	u16 picture_width;
+	u16 rate_buffer_size;
+	u16 slice_height;
+	u16 slice_width;
+	u8 supported_dsc_version;
+	u8 vbr_allowed;
+};
+struct vbt_dsc_param {
+	u8 dsc_support;
+	u8 valid_pps;
+	u8 block_prediction;
+	u8 panel_bpc;
+	u8 bit_depth;
+	u16 rate_buffer_size;
+	u16 slice_height;
+	u16 slice_width;
+	u8 dsc_version;
+	struct vesa_dsc_pps_data pps_data;
+};
+
 struct mipi_config {
 	u16 panel_id;
 
-- 
1.7.9.5