[Intel-gfx] [PATCH 01/15] drm/i915: Always program m2 fractional value on CHV

[Ville Syrjälä]

On Mon, Aug 17, 2015 at 07:49:41AM +0530, Deepak wrote:
> 
> 
> On 07/09/2015 02:15 AM, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > When fractional m2 divider isn't used on CHV the fractional part
> > is ignore by the hardware. Despite that, program the fractional
> > value (0 in this case) to the hardware register just to keep
> > things a bit more consistent. Might at least make register dumps
> > a bit less confusing when there isn't some stale fractional part
> > hanging around.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/intel_display.c | 3 +--
> >   1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 0b2ad76..3df9cb2 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7393,8 +7393,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> >   			1 << DPIO_CHV_N_DIV_SHIFT);
> >   
> >   	/* M2 fraction division */
> > -	if (bestm2_frac)
> > -		vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> > +	vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
> >   
> >   	/* M2 fraction division enable */
> >   	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> Since we do not use fractional m2 driver in chv, can we remove other 
> bestm2_frac used in chv pll function?
> like
> if (bestm2_frac)
>      dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> 
> &
> if (!bestm2_frac)
>      dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> 
> Do we need this?

We do use the fractional divider, when it's not 0.

-- 
Ville Syrjälä
Intel OTC