[Intel-gfx] [PATCH 11/16] drm/i915/bdw: don't enable FBC when pixel rate exceeds 95%

[Ville Syrjälä]

On Fri, Aug 14, 2015 at 06:34:16PM -0300, Paulo Zanoni wrote:
> BSpec says we shouldn't enable FBC on BDW when the pipe pixel rate
> exceeds 95% of the core display clock.

w/a db says HSW has the same issue, apparently it was found on HSW
originally. Actually it says BDW G0 would have it fixed. Bspec says
G1 in the w/a section. Not sure what to believe here. Better safe than
sorry probably and just do the w/a for BDW.

Also this has a name 'WaFbcExceedCdClockThreshold'

> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 1 +
>  drivers/gpu/drm/i915/intel_fbc.c | 8 ++++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f44d101..f8f3ed3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -946,6 +946,7 @@ struct i915_fbc {
>  		FBC_ROTATION, /* rotation is not supported */
>  		FBC_IN_DBG_MASTER, /* kernel debugger is active */
>  		FBC_BAD_STRIDE, /* stride is not supported */
> +		FBC_PIXEL_RATE, /* pixel rate is too big */
>  	} no_fbc_reason;
>  
>  	bool (*fbc_enabled)(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index cfd4cba..9dee0b5 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -503,6 +503,8 @@ const char *intel_no_fbc_reason_str(enum no_fbc_reason reason)
>  		return "Kernel debugger is active";
>  	case FBC_BAD_STRIDE:
>  		return "framebuffer stride not supported";
> +	case FBC_PIXEL_RATE:
> +		return "pixel rate is too big";
>  	default:
>  		MISSING_CASE(reason);
>  		return "unknown reason";
> @@ -850,6 +852,12 @@ static void __intel_fbc_update(struct drm_i915_private *dev_priv)
>  		goto out_disable;
>  	}
>  
> +	if (IS_BROADWELL(dev_priv) && ilk_pipe_pixel_rate(intel_crtc->config) >=
> +	    dev_priv->max_cdclk_freq * 95 / 100) {

That should be looking at the current cdclk, not the max. We should
probablt change our cdclk computations to include some headroom for
FBC/IPS when there aren't other factors that would preclude their use.

> +		set_no_fbc_reason(dev_priv, FBC_PIXEL_RATE);
> +		goto out_disable;
> +	}
> +
>  	if (intel_fbc_setup_cfb(intel_crtc)) {
>  		set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL);
>  		goto out_disable;
> -- 
> 2.4.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC