[Intel-gfx] [PATCH 1/5] agp/intel: Serialise after GTT updates

Daniel Vetter daniel at ffwll.ch
Fri Feb 6 00:32:29 PST 2015


On Thu, Feb 05, 2015 at 04:11:00PM -0800, Jesse Barnes wrote:
> On Wed, 14 Jan 2015 11:20:55 +0000
> Chris Wilson <chris at chris-wilson.co.uk> wrote:
> 
> > diff --git a/drivers/char/agp/intel-gtt.c
> > b/drivers/char/agp/intel-gtt.c index 92aa43fa8d70..15685ca39193 100644
> > --- a/drivers/char/agp/intel-gtt.c
> > +++ b/drivers/char/agp/intel-gtt.c
> > @@ -225,7 +225,7 @@ static int i810_insert_dcache_entries(struct
> > agp_memory *mem, off_t pg_start,
> > intel_private.driver->write_entry(addr, i, type);
> >  	}
> > -	readl(intel_private.gtt+i-1);
> > +	readl(intel_private.gtt+pg_start);
> 
> Any idea why?  This one scares me...  is it that the read is being
> serviced from the WC buffer w/o being flushed?  Or is the compiler
> optimizing the last read based on the previous write?
> 
> Writing a non-sequential address should also cause a flush, but I don't
> remember the rules for reads.  We should get this figured out while we
> have an easy way to reproduce and a willing tester.

Yeah agreed, but apparently a full mb(); is good enough too. So that's
what has landed.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


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