[Intel-gfx] [PATCH 4/7] drm/i915/skl: Updated the gen6_rps_limits function

Chris Wilson chris at chris-wilson.co.uk
Mon Feb 9 03:03:29 PST 2015


On Mon, Feb 09, 2015 at 10:26:33AM +0530, Akash Goel wrote:
> On Fri, 2015-02-06 at 15:43 +0000, Chris Wilson wrote:
> > On Fri, Feb 06, 2015 at 08:26:35PM +0530, akash.goel at intel.com wrote:
> > > From: Akash Goel <akash.goel at intel.com>
> > > 
> > > RP Interrupt Up/Down Frequency Limits register (A014) definition
> > > has changed for SKL. Updated the gen6_rps_limits function as per that
> > > 
> > > Signed-off-by: Akash Goel <akash.goel at intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_pm.c | 16 +++++++++++-----
> > >  1 file changed, 11 insertions(+), 5 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index 215b200..db24b48 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3623,7 +3623,7 @@ static void ironlake_disable_drps(struct drm_device *dev)
> > >   * ourselves, instead of doing a rmw cycle (which might result in us clearing
> > >   * all limits and the gpu stuck at whatever frequency it is at atm).
> > >   */
> > > -static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
> > > +static u32 get_rps_limits(struct drm_i915_private *dev_priv, u8 val)
> > 
> > Spurious name change, it doesn't seem to add anything or clear up any
> > confusion with vlv.
> Fine will keep the original name, thought would be better to give a
> generic name to the function and abstract the platform specific
> differences inside its definition. 

Generic would be intel_rps_limits(). I am wary of using get(), the
common idiom is for a getter to return ownership as well, e.g.
kref_get(), intel_uncore_forcewake_get(). Also outside of trivial getters
and setters, get is such a generic verb that I don't think it adds much
self-documentating value, especially when breaking established patterns.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre


More information about the Intel-gfx mailing list