[Intel-gfx] [PATCH 1/2] drm/i915: gen 9 h/w w/a Fix stepping check

[Daniel Vetter]

On Fri, Feb 06, 2015 at 11:52:42AM +0000, Damien Lespiau wrote:
> On Fri, Feb 06, 2015 at 11:30:03AM +0000, Nick Hoath wrote:
> > Fixed the stepping check on WaDisableDgMirrorFixInHalfSliceChicken5
> > to be for the correct SOC (Skylake)
> > 
> > Signed-off-by: Nick Hoath <nicholas.hoath at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 573b80f..fb71e33 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -886,7 +886,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> >  			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> >  
> > -	if (INTEL_REVID(dev) == SKL_REVID_A0) {
> > +	if (INTEL_REVID(dev) >= SKL_REVID_A0 &&
> > +	    INTEL_REVID(dev) <= SKL_REVID_B0) {
> 
>  x >= 0 && x <= 1 looks really better as x == 0 || x == 1

for pre-production w/a I don't really care all that much how they look,
we'll remove them anyway in a few months or so. For production stuff I
prefer we stick to how we do gen checks:
- gen >= 5 (read as gen5+)
- gen < 6 (read as pre-gen5)
Consistency to avoid accidentaly off-by-one and it seems to match what
Bspec uses, too.
> 
> Otherwise:
> 
> Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

Both merged, thanks for patches&review.
-Daniel
> 
> >  		/*
> >  		* WaDisableDgMirrorFixInHalfSliceChicken5:skl
> >  		* This is a pre-production w/a.
> > -- 
> > 2.1.1
> > 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch