[Intel-gfx] [PATCH] drm: Adding edp1.4 specific dpcd macros

[Jani Nikula]

On Thu, 19 Feb 2015, Todd Previte <tprevite at gmail.com> wrote:
> Just some formatting issues that need to be cleaned up. Otherwise the 
> definitions look correct according to the eDP 1.4 spec.

Actually the formatting seems to be in line with the rest of that
particular file.

BR,
Jani.

>
> -T
>
> On 2/19/15 12:46 AM, Sonika Jindal wrote:
>> Adding dpcd macros related to edp1.4 and link rates
>>
>> v2: Added DP_SUPPORTED_LINK_RATES macros
>>
>> Signed-off-by: Sonika Jindal <sonika.jindal at intel.com>
>> ---
>>   include/drm/drm_dp_helper.h |    8 ++++++++
>>   1 file changed, 8 insertions(+)
>>
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index 11f8c84..77a55e2 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -92,6 +92,9 @@
>>   # define DP_MSA_TIMING_PAR_IGNORED	    (1 << 6) /* eDP */
>>   # define DP_OUI_SUPPORT			    (1 << 7)
>>
>> +#define DP_SUPPORTED_LINK_RATES			0x010 /*eDP 1.4*/
>> +#define DP_MAX_SUPPORTED_RATES			0x8
>> +
> Extra blank line
>>   #define DP_I2C_SPEED_CAP		    0x00c    /* DPI */
>>   # define DP_I2C_SPEED_1K		    0x01
>>   # define DP_I2C_SPEED_5K		    0x02
>> @@ -101,6 +104,7 @@
>>   # define DP_I2C_SPEED_1M		    0x20
>>
>>   #define DP_EDP_CONFIGURATION_CAP            0x00d   /* XXX 1.2? */
>> +# define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
> Remove the space between # and define.
>>   #define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
>>
>>   /* Multiple stream transport */
>> @@ -221,6 +225,8 @@
>>   # define DP_UP_REQ_EN			    (1 << 1)
>>   # define DP_UPSTREAM_IS_SRC		    (1 << 2)
>>
>> +#define DP_LINK_RATE_SET			0x115
>> +
> Extra blank line
>>   #define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
>>   # define DP_PSR_ENABLE			    (1 << 0)
>>   # define DP_PSR_MAIN_LINK_ACTIVE	    (1 << 1)
>> @@ -332,6 +338,8 @@
>>   # define DP_SET_POWER_D3                    0x2
>>   # define DP_SET_POWER_MASK                  0x3
>>
>> +#define DP_EDP_DPCD_REV                          0x700
>> +
> Extra blank line
>>   #define DP_SIDEBAND_MSG_DOWN_REQ_BASE	    0x1000   /* 1.2 MST */
>>   #define DP_SIDEBAND_MSG_UP_REP_BASE	    0x1200   /* 1.2 MST */
>>   #define DP_SIDEBAND_MSG_DOWN_REP_BASE	    0x1400   /* 1.2 MST */
>
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-- 
Jani Nikula, Intel Open Source Technology Center