[Intel-gfx] [PATCH 2/6] drm/i915/bdw: Add support for DRRS to switch RR

[Rodrigo Vivi]

On Thu, Feb 19, 2015 at 10:15 PM, Ramalingam C <ramalingam.c at intel.com> wrote:
> Hi,
>
>
> On Thursday 19 February 2015 10:55 PM, Rodrigo Vivi wrote:
>>
>> On Fri, Feb 13, 2015 at 2:03 AM, Ramalingam C <ramalingam.c at intel.com>
>> wrote:
>>>
>>> From: Vandana Kannan <vandana.kannan at intel.com>
>>>
>>> For Broadwell, there is one instance of Transcoder MN values per
>>> transcoder.
>>> For dynamic switching between multiple refreshr rates, M/N values may be
>>> reprogrammed on the fly. Link N programming triggers update of all data
>>> and
>>> link M & N registers and the new M/N values will be used in the next
>>> frame
>>> that is output.
>>>
>>> V2: [By Ram]: intel_dp_set_m_n() is rewritten to accommodate
>>>          gen >= 8 [Rodrigo]
>>> V3: Coding style correction [Ram]
>>> V4: [By Ram] intel_dp_set_m_n modifications are moved into a
>>>          separate patch, retaining only DRRS related changes here
>>> [Rodrigo]
>>>
>>> Signed-off-by: Vandana Kannan <vandana.kannan at intel.com>
>>> Signed-off-by: Pradeep Bhat <pradeep.bhat at intel.com>
>>> Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/intel_dp.c |   16 ++++++++++++++--
>>>   1 file changed, 14 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_dp.c
>>> b/drivers/gpu/drm/i915/intel_dp.c
>>> index 868a07b..6ffbf57 100644
>>> --- a/drivers/gpu/drm/i915/intel_dp.c
>>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>>> @@ -4793,12 +4793,24 @@ static void intel_dp_set_drrs_state(struct
>>> drm_device *dev, int refresh_rate)
>>>                  return;
>>>          }
>>>
>>> -       if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
>>> +       if (INTEL_INFO(dev)->gen >= 8) {
>>> +               switch (index) {
>>> +               case DRRS_HIGH_RR:
>>> +                       intel_dp_set_m_n(intel_crtc, M1_N1);
>>> +                       break;
>>> +               case DRRS_LOW_RR:
>>> +                       intel_dp_set_m_n(intel_crtc, M2_N2);
>>> +                       break;
>>> +               case DRRS_MAX_RR:
>>
>> Why to redirect this to an error insted making MAX = HIGH?
>
> This DRRS state is decided within kernel based on the vrefresh requested.
> Hence this can't be out of HIGH/LOW.
> So this case can't occur. If it occurs I would like to report it as an
> error.

Thanks for the explanation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

>>
>>
>>> +               default:
>>> +                       DRM_ERROR("Unsupported refreshrate type\n");
>>> +               }
>>> +       } else if (INTEL_INFO(dev)->gen > 6) {
>>>                  reg = PIPECONF(intel_crtc->config->cpu_transcoder);
>>>                  val = I915_READ(reg);
>>> +
>>>                  if (index > DRRS_HIGH_RR) {
>>>                          val |= PIPECONF_EDP_RR_MODE_SWITCH;
>>> -                       intel_dp_set_m_n(intel_crtc);
>>>                  } else {
>>>                          val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
>>>                  }
>>> --
>>> 1.7.9.5
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx at lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>
> --
> Ram
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br