[Intel-gfx] [PATCH 0/9] drm/i915: Check pixel clock when setting mode

[Chris Wilson]

On Fri, Jul 03, 2015 at 02:35:48PM +0300, Mika Kahola wrote:
> From EDID we can read and request higher pixel clock than
> our HW can support. This set of patches add checks if
> requested pixel clock is lower than the one supported by the HW.
> The requested mode is discarded if we cannot support the requested
> pixel clock. For example for Cherryview
> 
> 'cvt 2560 1600 60' gives
> 
> # 2560x1600 59.99 Hz (CVT 4.10MA) hsync: 99.46 kHz; pclk: 348.50 MHz
> Modeline "2560x1600_60.00"  348.50  2560 2760 3032 3504  1600 1603 1609 1658 -hsync +vsync
> 
> where pixel clock 348.50 MHz is higher than the supported 304 MHz.
> 
> The checks are implemented for DisplayPort, HDMI, LVDS, DVO, SDVO, DSI,
> CRT, TV, and DP-MST.

Why do I get the feeling that there was a lot of duplicated code?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre