[Intel-gfx] [PATCH 0/6] Redesign the dmc firmware loading.

[Animesh Manna]

v1: Based on review comments from Daniel following changes are done.
- More focus is given for better synchronization.
- Replaced async firmware loading by using request_firmawre() call.
- Prevented entering in dc5/dc6 while firmware loading in process.
Now register programming for dc5/dc6 always will happen followed
by firmware loading.
- Removed the csr-lock and csr-state which was used before.
- Added a async work which is responsible for both loading the
firmware and register programming for dc5/dc6.
- Added flush_work() to explicitly synchronize the async work
during suspend and driver unloading.
- Corrected the sanity check for mmio address of csr (Requested by Imre).
- Removed assert call of csr during disabling dc6 (Requested by Damien).


Animesh Manna (6):
  drm/i915/gen9: Removed csr-lock and csr-state
  drm/i915/gen9: Added a async work for fw-loading and dc5/dc6
    programming
  drm/i915/gen9: Replaced request_firmware_nowait() by
    request_firmware().
  drm/i915/gen9: Added dmc_present flag to check firmware loading
    status.
  drm/i915/skl: Removed assert for csr-fw-loading during disabling dc6.
  drm/i915/gen9: Corrected the sanity check of mmio address range for
    csr.

 drivers/gpu/drm/i915/i915_dma.c         |   1 -
 drivers/gpu/drm/i915/i915_drv.c         |  10 +--
 drivers/gpu/drm/i915/i915_drv.h         |  16 ++--
 drivers/gpu/drm/i915/intel_csr.c        | 144 +++++++++++---------------------
 drivers/gpu/drm/i915/intel_drv.h        |   5 +-
 drivers/gpu/drm/i915/intel_runtime_pm.c |  62 +++++++-------
 6 files changed, 92 insertions(+), 146 deletions(-)

-- 
2.0.2