[Intel-gfx] [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV

[Arun R Murthy]

On Thursday 11 June 2015 07:01 PM, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV
> docs got updated at some point to say that we need to align them to
> 128k, just like we do on gen4.
>
> So far I've seen the problem manifest when the stride is an odd multiple
> of 512 bytes, and the surface address meets the following pattern
> '(addr & 0xf000) == 0x1000' (also == 0x2000 is problematic on VLV). The
> result is a starcase effect (so some pages get dropped maybe?), with a
> few pages here and there clearly getting scannout out at the wrong position.
>
> I've not actually been able to reproduce this problem on gen4, so it's
> not clear of the issue is any way related to the 128k restrictions
> supposedly inherited from gen4. But let's hope the 128k alignment is
> sufficient to hide it all.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy at intel.com>

Thanks and Regards,
Arun R Murthy
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