[Intel-gfx] [PATCH v4 4/6] drm/i915/gen8: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaround

[Chris Wilson]

On Tue, Jun 16, 2015 at 08:25:23PM +0100, Arun Siluvery wrote:
> +	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
> +	if (IS_BROADWELL(ring->dev)) {
> +		struct drm_i915_private *dev_priv = ring->dev->dev_private;

dev_priv = to_i915(ring->dev);

> +
> +		cmd[index++] = MI_LOAD_REGISTER_IMM(1);
> +		cmd[index++] = GEN8_L3SQCREG4;
> +		cmd[index++] = I915_READ(GEN8_L3SQCREG4) |
> +			GEN8_LQSC_FLUSH_COHERENT_LINES;

Read the reg once, it is clearer that way.

> +
> +		cmd[index++] = GFX_OP_PIPE_CONTROL(6);
> +		cmd[index++] = PIPE_CONTROL_CS_STALL |
> +			PIPE_CONTROL_DC_FLUSH_ENABLE;
> +		cmd[index++] = 0;
> +		cmd[index++] = 0;
> +		cmd[index++] = 0;
> +		cmd[index++] = 0;
> +
> +		cmd[index++] = MI_LOAD_REGISTER_IMM(1);
> +		cmd[index++] = GEN8_L3SQCREG4;
> +		cmd[index++] = I915_READ(GEN8_L3SQCREG4) &
> +			~GEN8_LQSC_FLUSH_COHERENT_LINES;
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre