[Intel-gfx] [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h

[Daniel Vetter]

On Fri, Jun 26, 2015 at 06:53:49AM -0700, Chandra Konduru wrote:
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
> 
> Signed-off-by: Chandra Konduru <chandra.konduru at intel.com>

Do we have an igt which provokes underruns and hence can test this
automatically? Very tall/narrow buffers should do it I think.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_pm.c |   32 ++++++++++++++++++++++++++++----
>  1 file changed, 28 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ea3e435..767313b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  	enum pipe pipe = intel_crtc->pipe;
>  	struct drm_plane *plane;
>  	struct drm_framebuffer *fb;
> +	struct intel_plane_state *plane_state;
> +	int src_w, src_h;
>  	int i = 1; /* Index for sprite planes start */
>  
>  	p->active = intel_crtc->active;
> @@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  		p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
>  
>  		fb = crtc->primary->state->fb;
> +		plane_state = to_intel_plane_state(crtc->primary->state);
>  		/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
>  		if (fb) {
>  			p->plane[0].enabled = true;
> @@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
>  			p->plane[0].y_bytes_per_pixel = 0;
>  			p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
>  		}
> -		p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> -		p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
> +
> +		if (drm_rect_width(&plane_state->src)) {
> +			src_w = drm_rect_width(&plane_state->src) >> 16;
> +			src_h = drm_rect_height(&plane_state->src) >> 16;
> +		} else {
> +			src_w = intel_crtc->config->pipe_src_w;
> +			src_h = intel_crtc->config->pipe_src_h;
> +		}
> +
> +		if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
> +			p->plane[0].horiz_pixels = src_h;
> +			p->plane[0].vert_pixels = src_w;
> +		} else {
> +			p->plane[0].horiz_pixels = src_w;
> +			p->plane[0].vert_pixels = src_h;
> +		}
>  		p->plane[0].rotation = crtc->primary->state->rotation;
>  
>  		fb = crtc->cursor->state->fb;
> @@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
>  
>  	intel_plane->wm.enabled = enabled;
>  	intel_plane->wm.scaled = scaled;
> -	intel_plane->wm.horiz_pixels = sprite_width;
> -	intel_plane->wm.vert_pixels = sprite_height;
> +
> +	if (intel_rotation_90_or_270(plane->state->rotation)) {
> +		intel_plane->wm.horiz_pixels = sprite_height;
> +		intel_plane->wm.vert_pixels = sprite_width;
> +	} else {
> +		intel_plane->wm.horiz_pixels = sprite_width;
> +		intel_plane->wm.vert_pixels = sprite_height;
> +	}
> +
>  	intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
>  
>  	/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
> -- 
> 1.7.9.5
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch