[Intel-gfx] [PATCH] drm/i915: Check lane sharing between pipes B & C using atomic state

[shuang.he at intel.com]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he at intel.com)
Task id: 6087
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                 -2              270/270              268/270
ILK                                  303/303              303/303
SNB                                  304/304              304/304
IVB                                  337/337              337/337
BYT                                  287/287              287/287
HSW                                  361/361              361/361
BDW                                  309/309              309/309
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt at gem_userptr_blits@coherency-sync      CRASH(1)PASS(2)      CRASH(1)PASS(1)
*PNV  igt at gem_tiled_pread_pwrite      PASS(3)      FAIL(1)PASS(1)
Note: You need to pay more attention to line start with '*'