[Intel-gfx] [PATCH 00/16] 48b PPGTT

[Michel Thierry]

In order expand the GPU address space, a 4th level translation is added, the
Page Map Level 4 (PML4). This PML4 has 256 PML4 Entries (PML4E), PML4[0-255],
each pointing to a PDP. All the existing "dynamic alloc ppgtt" functions are
used, only adding the 4th level changes. I also updated some remaining
variables that were 32b only.

There are 2 hardware workarounds needed to allow correct operation with 48b
addresses (Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset). I added a
flag (EXEC_OBJECT_NEEDS_32BADDRESS) that will indicate if a given object must be
allocated inside the first 4 PDPs, and in order to limit the chances of having
the first 4GB already full, objects not requiring this workaround start at an
offset of this range. Another option would be to send the DRM_MM_CREATE_TOP flag. 
I'm also including an igt test for this change.

This feature is only available in BDW and Gen9, and requires LRC submission
mode (execlists) and setting i915.enable_ppgtt=3.

Also note that this expanded address space is only available for full PPGTT,
aliasing PPGTT remains 32b.

Finally, Mika has sent some PPGTT clean up patches, which will conflict with
these. I'm open to rebase these patches after Mika's, or update his patches
after the 48b ones. Please let me know which option is better.

Michel Thierry (16):
  drm/i915: Remove unnecessary gen8_clamp_pd
  drm/i915/gen8: Make pdp allocation more dynamic
  drm/i915/gen8: Abstract PDP usage
  drm/i915/gen8: Add dynamic page trace events
  drm/i915/gen8: implement alloc/free for 4lvl
  drm/i915/gen8: Add 4 level switching infrastructure and lrc support
  drm/i915/gen8: Generalize PTE writing for GEN8 PPGTT
  drm/i915: Plumb sg_iter through va allocation ->maps
  drm/i915/gen8: Add 4 level support in insert_entries and clear_range
  drm/i915/gen8: Initialize PDPs
  drm/i915: Expand error state's address width to 64b
  drm/i915/gen8: Add ppgtt info and debug_dump
  drm/i915: object size needs to be u64
  drm/i915: Check against correct user_size limit in 48b ppgtt mode
  drm/i915: Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset
  drm/i915/gen8: Flip the 48b switch

 drivers/gpu/drm/i915/i915_debugfs.c        |  18 +-
 drivers/gpu/drm/i915/i915_drv.h            |  12 +-
 drivers/gpu/drm/i915/i915_gem.c            |  16 +-
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |   3 +
 drivers/gpu/drm/i915/i915_gem_gtt.c        | 740 ++++++++++++++++++++++++-----
 drivers/gpu/drm/i915/i915_gem_gtt.h        |  70 ++-
 drivers/gpu/drm/i915/i915_gem_userptr.c    |  12 +-
 drivers/gpu/drm/i915/i915_gpu_error.c      |  17 +-
 drivers/gpu/drm/i915/i915_params.c         |   2 +-
 drivers/gpu/drm/i915/i915_reg.h            |   1 +
 drivers/gpu/drm/i915/i915_trace.h          |  16 +
 drivers/gpu/drm/i915/intel_lrc.c           |  50 +-
 include/uapi/drm/i915_drm.h                |   3 +-
 13 files changed, 797 insertions(+), 163 deletions(-)

-- 
2.4.0