[Intel-gfx] [PATCH 25/31] drm/i915: Send TP1 TP2/3 even when panel claims no NO_TRAIN_ON_EXIT.

Vivi, Rodrigo rodrigo.vivi at intel.com
Tue Nov 10 07:42:14 PST 2015


On Mon, 2015-11-09 at 12:39 +0200, Jani Nikula wrote:
> On Thu, 05 Nov 2015, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> > On the commit 3301d4092106 ("drm/i915: PSR: Fix 
> > DP_PSR_NO_TRAIN_ON_EXIT logic")'
> > we already had identified that DP_PSR_NO_TRAIN_ON_EXIT
> > doesn't mean we shouldn't send TPS patterns, however we start 
> > sending the
> > minimal TP1 as possible and no TP2.
> > 
> > For most of the panels this is ok, but we found a reported case 
> > where
> > this is not true and panel keeps frozen without updating the screen 
> > for a while.
> > 
> > We could just get this case after patch "PSR: Don't Skip aux 
> > handshake on
> > DP_PSR_NO_TRAIN_ON_EXIT." is applied since that one fix the
> > hard freeze on this kind of panels.
> > 
> > Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436#c19
> > 
> > Cc: Ivan Mitev <ivan.mitev at gmail.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> 
> Ditto. Do these really depend on all the other patches in the series?

No, but the last patch in the series depend on this and on the rest of
the series.

> 
> Jani.
> 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 4 ----
> >  1 file changed, 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c 
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 4e88e2e..ee426ea 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -259,10 +259,6 @@ static void hsw_psr_enable_source(struct 
> > intel_dp *intel_dp)
> >  	const uint32_t link_entry_time = 
> > EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> >  
> >  	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
> > -		/* It doesn't mean we shouldn't send TPS patters, 
> > so let's
> > -		   send the minimal TP1 possible and skip TP2. */
> > -		val |= EDP_PSR_TP1_TIME_100us;
> > -		val |= EDP_PSR_TP2_TP3_TIME_0us;
> >  		/* Sink should be able to train with the 5 or 6 
> > idle patterns */
> >  		idle_frames += 4;
> >  	}
> 


More information about the Intel-gfx mailing list