[Intel-gfx] [PATCH 155/190] drm/i915: Merge legacy+execlists context structs
Chris Wilson
chris at chris-wilson.co.uk
Mon Jan 11 03:00:56 PST 2016
struct intel_context contains two substructs, one for the legacy RCS and
one for every execlists engine. Since legacy RCS is a subset of the
execlists engine support, just combine the two substructs.
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 34 +++++---------
drivers/gpu/drm/i915/i915_drv.h | 10 +----
drivers/gpu/drm/i915/i915_gem_context.c | 78 ++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_lrc.c | 25 -----------
drivers/gpu/drm/i915/intel_lrc.h | 1 -
5 files changed, 54 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4cd05b730b4c..558d79b63e6c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -179,13 +179,6 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}
-static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
-{
- seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
- seq_putc(m, ctx->remap_slice ? 'R' : 'r');
- seq_putc(m, ' ');
-}
-
static int i915_gem_object_list_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = m->private;
@@ -1954,10 +1947,6 @@ static int i915_context_status(struct seq_file *m, void *unused)
return ret;
list_for_each_entry(ctx, &dev_priv->context_list, link) {
- if (!i915.enable_execlists &&
- ctx->legacy_hw_ctx.rcs_state == NULL)
- continue;
-
seq_puts(m, "HW context ");
if (ctx->pid) {
struct task_struct *task;
@@ -1970,21 +1959,18 @@ static int i915_context_status(struct seq_file *m, void *unused)
}
} else
seq_puts(m, "(kernel) ");
- describe_ctx(m, ctx);
- if (i915.enable_execlists) {
+ seq_putc(m, ctx->remap_slice ? 'R' : 'r');
+ seq_putc(m, '\n');
+
+ for_each_ring(ring, dev_priv, i) {
+ seq_printf(m, "%s: ", ring->name);
+ seq_putc(m, ctx->engine[i].initialised ? 'I' : 'i');
+ if (ctx->engine[i].state)
+ describe_obj(m, ctx->engine[i].state);
+ if (ctx->engine[i].ring)
+ describe_ctx_ring(m, ctx->engine[i].ring);
seq_putc(m, '\n');
- for_each_ring(ring, dev_priv, i) {
- seq_printf(m, "%s: ", ring->name);
- if (ctx->engine[i].state)
- describe_obj(m, ctx->engine[i].state);
- if (ctx->engine[i].ring)
- describe_ctx_ring(m,
- ctx->engine[i].ring);
- seq_putc(m, '\n');
- }
- } else {
- describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
}
seq_putc(m, '\n');
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dcff2f2066d0..917686eed962 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -885,15 +885,7 @@ struct intel_context {
#define CONTEXT_NO_ZEROMAP (1<<0)
#define CONTEXT_NO_ERROR_CAPTURE (1<<1)
- /* Legacy ring buffer submission */
- struct {
- struct drm_i915_gem_object *rcs_state;
- struct i915_vma *rcs_vma;
- bool initialized;
- } legacy_hw_ctx;
-
- /* Execlists */
- struct {
+ struct intel_context_engine {
struct drm_i915_gem_object *state;
struct i915_vma *vma;
struct intel_ring *ring;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b57112db1c3f..f261d9e0929d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -136,17 +136,25 @@ static int get_context_size(struct drm_device *dev)
void i915_gem_context_free(struct kref *ctx_ref)
{
struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
+ int i;
trace_i915_context_free(ctx);
GEM_BUG_ON(!ctx->closed);
- if (i915.enable_execlists)
- intel_lr_context_free(ctx);
+ for (i = 0; i < I915_NUM_RINGS; i++) {
+ struct intel_context_engine *ce = &ctx->engine[i];
- i915_ppgtt_put(ctx->ppgtt);
+ if (ce->state == NULL)
+ continue;
+
+ WARN_ON(ce->pin_count);
+ if (ce->ring)
+ intel_ring_free(ce->ring);
- if (ctx->legacy_hw_ctx.rcs_state)
- drm_gem_object_unreference(&ctx->legacy_hw_ctx.rcs_state->base);
+ drm_gem_object_unreference(&ce->state->base);
+ }
+
+ i915_ppgtt_put(ctx->ppgtt);
put_pid(ctx->pid);
list_del(&ctx->link);
@@ -245,7 +253,7 @@ __create_hw_context(struct drm_device *dev,
ret = PTR_ERR(obj);
goto err_out;
}
- ctx->legacy_hw_ctx.rcs_state = obj;
+ ctx->engine[RCS].state = obj;
}
/* Default context will never have a file_priv */
@@ -331,20 +339,21 @@ void i915_gem_context_reset(struct drm_device *dev)
struct intel_engine_cs *ring = &dev_priv->ring[i];
struct intel_context *lctx = ring->last_context;
- if (lctx) {
- if (lctx->legacy_hw_ctx.rcs_vma) {
- i915_vma_unpin(lctx->legacy_hw_ctx.rcs_vma);
- lctx->legacy_hw_ctx.rcs_vma = NULL;
- }
+ /* Force the GPU state to be reinitialised on enabling */
+ if (dev_priv->kernel_context)
+ dev_priv->kernel_context->engine[i].initialised = false;
+
+ if (lctx == NULL)
+ continue;
- i915_gem_context_unreference(lctx);
- ring->last_context = NULL;
+ if (lctx->engine[i].vma) {
+ i915_vma_unpin(lctx->engine[i].vma);
+ lctx->engine[i].vma = NULL;
}
- }
- /* Force the GPU state to be reinitialised on enabling */
- if (dev_priv->kernel_context)
- dev_priv->kernel_context->legacy_hw_ctx.initialized = false;
+ i915_gem_context_unreference(lctx);
+ ring->last_context = NULL;
+ }
}
int i915_gem_context_init(struct drm_device *dev)
@@ -384,7 +393,7 @@ int i915_gem_context_init(struct drm_device *dev)
return PTR_ERR(ctx);
}
- if (ctx->legacy_hw_ctx.rcs_state) {
+ if (ctx->engine[RCS].state) {
u32 alignment = get_context_alignment(dev);
struct i915_vma *vma;
@@ -395,7 +404,7 @@ int i915_gem_context_init(struct drm_device *dev)
* be available. To avoid this we always pin the default
* context.
*/
- vma = i915_gem_object_ggtt_pin(ctx->legacy_hw_ctx.rcs_state,
+ vma = i915_gem_object_ggtt_pin(ctx->engine[RCS].state,
NULL, 0, alignment, PIN_HIGH);
if (IS_ERR(vma)) {
DRM_ERROR("Failed to pinned default global context (error %d)\n",
@@ -419,7 +428,7 @@ void i915_gem_context_fini(struct drm_device *dev)
struct intel_context *dctx = dev_priv->kernel_context;
int i;
- if (dctx->legacy_hw_ctx.rcs_state) {
+ if (!i915.enable_execlists) {
/* The only known way to stop the gpu from accessing the hw context is
* to reset it. Do this as the very last operation to avoid confusing
* other code, leading to spurious errors. */
@@ -434,13 +443,13 @@ void i915_gem_context_fini(struct drm_device *dev)
WARN_ON(!dev_priv->ring[RCS].last_context);
if (dev_priv->ring[RCS].last_context == dctx) {
/* Fake switch to NULL context */
- WARN_ON(dctx->legacy_hw_ctx.rcs_vma->active);
- i915_vma_unpin(dctx->legacy_hw_ctx.rcs_vma);
+ WARN_ON(dctx->engine[RCS].vma->active);
+ i915_vma_unpin(dctx->engine[RCS].vma);
i915_gem_context_unreference(dctx);
dev_priv->ring[RCS].last_context = NULL;
}
- i915_vma_unpin(dctx->legacy_hw_ctx.rcs_vma);
+ i915_vma_unpin(dctx->engine[RCS].vma);
}
for (i = 0; i < I915_NUM_RINGS; i++) {
@@ -560,8 +569,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(ring, MI_NOOP);
intel_ring_emit(ring, MI_SET_CONTEXT);
- intel_ring_emit(ring,
- req->ctx->legacy_hw_ctx.rcs_vma->node.start | flags);
+ intel_ring_emit(ring, req->ctx->engine[RCS].vma->node.start | flags);
/*
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
* WaMiSetContext_Hang:snb,ivb,vlv
@@ -685,12 +693,12 @@ static int do_switch(struct drm_i915_gem_request *req)
u32 alignment = get_context_alignment(engine->dev);
struct i915_vma *vma;
- vma = i915_gem_object_ggtt_pin(to->legacy_hw_ctx.rcs_state,
+ vma = i915_gem_object_ggtt_pin(to->engine[RCS].state,
NULL, 0, alignment, PIN_HIGH);
if (IS_ERR(vma))
return PTR_ERR(vma);
- to->legacy_hw_ctx.rcs_vma = vma;
+ to->engine[RCS].vma = vma;
if (WARN_ON(!(vma->bound & GLOBAL_BIND))) {
ret = -ENODEV;
@@ -737,11 +745,11 @@ static int do_switch(struct drm_i915_gem_request *req)
*
* XXX: We need a real interface to do this instead of trickery.
*/
- ret = i915_gem_object_set_to_gtt_domain(to->legacy_hw_ctx.rcs_state, false);
+ ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false);
if (ret)
goto unpin_out;
- if (!to->legacy_hw_ctx.initialized || i915_gem_context_is_default(to)) {
+ if (!to->engine[RCS].initialised || i915_gem_context_is_default(to)) {
hw_flags |= MI_RESTORE_INHIBIT;
/* NB: If we inhibit the restore, the context is not allowed to
* die because future work may end up depending on valid address
@@ -790,13 +798,13 @@ static int do_switch(struct drm_i915_gem_request *req)
to->remap_slice &= ~(1<<i);
}
- if (!to->legacy_hw_ctx.initialized) {
+ if (!to->engine[RCS].initialised) {
if (engine->init_context) {
ret = engine->init_context(req);
if (ret)
goto unpin_out;
}
- to->legacy_hw_ctx.initialized = true;
+ to->engine[RCS].initialised = true;
}
/* The backing object for the context is done after switching to the
@@ -813,9 +821,9 @@ static int do_switch(struct drm_i915_gem_request *req)
* able to defer doing this until we know the object would be
* swapped, but there is no way to do that yet.
*/
- i915_vma_move_to_active(from->legacy_hw_ctx.rcs_vma, req, 0);
+ i915_vma_move_to_active(from->engine[RCS].vma, req, 0);
/* obj is kept alive until the next request by its active ref */
- i915_vma_unpin(from->legacy_hw_ctx.rcs_vma);
+ i915_vma_unpin(from->engine[RCS].vma);
i915_gem_context_unreference(from);
}
@@ -827,7 +835,7 @@ done:
unpin_out:
if (engine->id == RCS)
- i915_vma_unpin(to->legacy_hw_ctx.rcs_vma);
+ i915_vma_unpin(to->engine[RCS].vma);
return ret;
}
@@ -851,7 +859,7 @@ int i915_switch_context(struct drm_i915_gem_request *req)
WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
- if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
+ if (req->ctx->engine[RCS].state == NULL) { /* We have the fake context */
struct intel_engine_cs *engine = req->engine;
if (req->ctx != engine->last_context) {
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 68d06ab6acdc..c2a45f48da66 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1858,30 +1858,6 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
}
/**
- * intel_lr_context_free() - free the LRC specific bits of a context
- * @ctx: the LR context to free.
- *
- * The real context freeing is done in i915_gem_context_free: this only
- * takes care of the bits that are LRC related: the per-engine backing
- * objects and the logical ringbuffer.
- */
-void intel_lr_context_free(struct intel_context *ctx)
-{
- int i;
-
- for (i = 0; i < I915_NUM_RINGS; i++) {
- struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
-
- if (ctx_obj) {
- WARN_ON(ctx->engine[i].pin_count);
-
- intel_ring_free(ctx->engine[i].ring);
- drm_gem_object_unreference(&ctx_obj->base);
- }
- }
-}
-
-/**
* intel_lr_context_size() - return the size of the context for an engine
* @ring: which engine to find the context size for
*
@@ -1958,7 +1934,6 @@ static int execlists_context_deferred_alloc(struct intel_context *ctx,
struct intel_ring *ring;
int ret;
- WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
WARN_ON(ctx->engine[engine->id].state);
context_size = round_up(intel_lr_context_size(engine), 4096);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index a454372fe660..28ac50494b1e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -67,7 +67,6 @@ int intel_logical_rings_init(struct drm_device *dev);
#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
-void intel_lr_context_free(struct intel_context *ctx);
uint32_t intel_lr_context_size(struct intel_engine_cs *ring);
void intel_lr_context_unpin(struct intel_context *ctx,
struct intel_engine_cs *engine);
--
2.7.0.rc3
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