[Intel-gfx] [PATCH v2 04/12] drm/i915: Extract BXT DIMM helpers

[Jani Nikula]

On Tue, 26 Feb 2019, Ville Syrjala <ville.syrjala at linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Polish the bxt DIMM parsing by extracting a few small helpers.
>
> v2: Use struct dram_dimm_info
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.c | 93 ++++++++++++++++++++++-----------
>  1 file changed, 62 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d84f3485e775..f948d475bdf4 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1243,6 +1243,59 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> +static int bxt_get_dimm_size(u32 val)
> +{
> +	switch (val & BXT_DRAM_SIZE_MASK) {
> +	case BXT_DRAM_SIZE_4GB:
> +		return 4;
> +	case BXT_DRAM_SIZE_6GB:
> +		return 6;
> +	case BXT_DRAM_SIZE_8GB:
> +		return 8;
> +	case BXT_DRAM_SIZE_12GB:
> +		return 12;
> +	case BXT_DRAM_SIZE_16GB:
> +		return 16;
> +	default:
> +		MISSING_CASE(val);
> +		return 0;
> +	}
> +}
> +
> +static int bxt_get_dimm_width(u32 val)
> +{
> +	if (!bxt_get_dimm_size(val))
> +		return 0;
> +
> +	val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
> +
> +	return 8 << val;
> +}
> +
> +static int bxt_get_dimm_ranks(u32 val)
> +{
> +	if (!bxt_get_dimm_size(val))
> +		return 0;
> +
> +	switch (val & BXT_DRAM_RANK_MASK) {
> +	case BXT_DRAM_RANK_SINGLE:
> +		return 1;
> +	case BXT_DRAM_RANK_DUAL:
> +		return 2;
> +	default:
> +		MISSING_CASE(val);
> +		return 0;
> +	}
> +}
> +
> +static void bxt_get_dimm_info(struct dram_dimm_info *dimm,
> +			      u32 val)
> +{
> +	dimm->size = bxt_get_dimm_size(val);
> +	dimm->width = bxt_get_dimm_width(val);
> +	dimm->ranks = bxt_get_dimm_ranks(val);
> +}
> +
>  static int
>  bxt_get_dram_info(struct drm_i915_private *dev_priv)
>  {
> @@ -1271,41 +1324,19 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
>  	 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
>  	 */
>  	for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
> -		u8 size, width, ranks;
> -		u32 tmp;
> +		struct dram_dimm_info dimm;
>  
>  		val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
>  		if (val == 0xFFFFFFFF)
>  			continue;
>  
>  		dram_info->num_channels++;
> -		tmp = val & BXT_DRAM_RANK_MASK;
> -
> -		if (tmp == BXT_DRAM_RANK_SINGLE)
> -			ranks = 1;
> -		else if (tmp == BXT_DRAM_RANK_DUAL)
> -			ranks = 2;
> -		else
> -			ranks = 0;
> -
> -		tmp = val & BXT_DRAM_SIZE_MASK;
> -		if (tmp == BXT_DRAM_SIZE_4GB)
> -			size = 4;
> -		else if (tmp == BXT_DRAM_SIZE_6GB)
> -			size = 6;
> -		else if (tmp == BXT_DRAM_SIZE_8GB)
> -			size = 8;
> -		else if (tmp == BXT_DRAM_SIZE_12GB)
> -			size = 12;
> -		else if (tmp == BXT_DRAM_SIZE_16GB)
> -			size = 16;
> -		else
> -			size = 0;
> -
> -		tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
> -		width = (1 << tmp) * 8;
> -		DRM_DEBUG_KMS("dram size:%dGB width:X%d ranks:%d\n",
> -			      size, width, ranks);
> +
> +		bxt_get_dimm_info(&dimm, val);
> +
> +		DRM_DEBUG_KMS("CH%d DIMM size: %d GB, width: X%d, ranks: %d\n",
> +			      i - BXT_D_CR_DRP0_DUNIT_START,
> +			      dimm.size, dimm.width, dimm.ranks);
>  
>  		/*
>  		 * If any of the channel is single rank channel,
> @@ -1313,8 +1344,8 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
>  		 * memory, so consider single rank memory.
>  		 */
>  		if (dram_info->ranks == 0)
> -			dram_info->ranks = ranks;
> -		else if (ranks == 1)
> +			dram_info->ranks = dimm.ranks;
> +		else if (dimm.ranks == 1)
>  			dram_info->ranks = 1;
>  	}

-- 
Jani Nikula, Intel Open Source Graphics Center