[Intel-gfx] [PATCH v2] drm/i915: Fix PSR2 selective update corruption after PSR1 setup

[Dhinakaran Pandiyan]

On Thu, 2019-03-14 at 16:01 -0700, José Roberto de Souza wrote:
> There is probably a issue in DMC firmwares(icl_dmc_ver1_07.bin and
> kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to fail
nit: instead of "fail", it is better to document what you see visually
- freeze, flicker, corruption etc.

>  after
> exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so for now
> lets workaround the issue by cleaning PSR_CTL before enable PSR2.
> 
> v2:
> - Updated commit description and comment to state that it may be
> a DMC firmware issue (Rodrigo)
> - No need to RMW, let's write 0 to PSR_CTL(Dhinakaran)

Based on the discussion with José offline, this work around sounds
reasonable to have until we have answers to whether this is a DMC
issue.
 
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 7d570a45fc17..10bf70e521b6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -531,6 +531,14 @@ static void hsw_activate_psr2(struct intel_dp
> *intel_dp)
>  	else
>  		val |= EDP_PSR2_TP2_TIME_2500us;
>  
> +	/*
> +	 * FIXME: There is probably a issue in DMC
> firmwares(icl_dmc_ver1_07.bin
> +	 * and kbl_dmc_ver1_04.bin at least) that causes PSR2 SU to 
nit: Expand SU to selective update, I am not sure how familiar others
with these acronyms.

> fail after
> +	 * exiting DC6 if EDP_PSR_TP1_TP3_SEL is kept in PSR_CTL, so
> for now
> +	 * lets workaround the issue by cleaning PSR_CTL before enable 
clearing*
> PSR2.
> +	 */
> +	I915_WRITE(EDP_PSR_CTL, 0);
> +
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
>