[Intel-gfx] [PATCH] drm/i915: Engine relative MMIO
kbuild test robot
lkp at intel.com
Wed Mar 20 11:39:33 UTC 2019
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/John-C-Harrison-Intel-com/drm-i915-Engine-relative-MMIO/20190320-141647
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-s0-201911 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
In file included from drivers/gpu/drm/i915/intel_workarounds.c:1260:0:
drivers/gpu/drm/i915/selftests/intel_workarounds.c: In function 'check_dirty_whitelist':
>> drivers/gpu/drm/i915/selftests/intel_workarounds.c:520:12: error: implicit declaration of function 'MI_LOAD_REGISTER_IMM' [-Werror=implicit-function-declaration]
*cs++ = MI_LOAD_REGISTER_IMM(1);
^~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +/MI_LOAD_REGISTER_IMM +520 drivers/gpu/drm/i915/selftests/intel_workarounds.c
34ae8455 Chris Wilson 2019-03-01 441
34ae8455 Chris Wilson 2019-03-01 442 static int check_dirty_whitelist(struct i915_gem_context *ctx,
34ae8455 Chris Wilson 2019-03-01 443 struct intel_engine_cs *engine)
34ae8455 Chris Wilson 2019-03-01 444 {
34ae8455 Chris Wilson 2019-03-01 445 const u32 values[] = {
34ae8455 Chris Wilson 2019-03-01 446 0x00000000,
34ae8455 Chris Wilson 2019-03-01 447 0x01010101,
34ae8455 Chris Wilson 2019-03-01 448 0x10100101,
34ae8455 Chris Wilson 2019-03-01 449 0x03030303,
34ae8455 Chris Wilson 2019-03-01 450 0x30300303,
34ae8455 Chris Wilson 2019-03-01 451 0x05050505,
34ae8455 Chris Wilson 2019-03-01 452 0x50500505,
34ae8455 Chris Wilson 2019-03-01 453 0x0f0f0f0f,
34ae8455 Chris Wilson 2019-03-01 454 0xf00ff00f,
34ae8455 Chris Wilson 2019-03-01 455 0x10101010,
34ae8455 Chris Wilson 2019-03-01 456 0xf0f01010,
34ae8455 Chris Wilson 2019-03-01 457 0x30303030,
34ae8455 Chris Wilson 2019-03-01 458 0xa0a03030,
34ae8455 Chris Wilson 2019-03-01 459 0x50505050,
34ae8455 Chris Wilson 2019-03-01 460 0xc0c05050,
34ae8455 Chris Wilson 2019-03-01 461 0xf0f0f0f0,
34ae8455 Chris Wilson 2019-03-01 462 0x11111111,
34ae8455 Chris Wilson 2019-03-01 463 0x33333333,
34ae8455 Chris Wilson 2019-03-01 464 0x55555555,
34ae8455 Chris Wilson 2019-03-01 465 0x0000ffff,
34ae8455 Chris Wilson 2019-03-01 466 0x00ff00ff,
34ae8455 Chris Wilson 2019-03-01 467 0xff0000ff,
34ae8455 Chris Wilson 2019-03-01 468 0xffff00ff,
34ae8455 Chris Wilson 2019-03-01 469 0xffffffff,
34ae8455 Chris Wilson 2019-03-01 470 };
34ae8455 Chris Wilson 2019-03-01 471 struct i915_vma *scratch;
34ae8455 Chris Wilson 2019-03-01 472 struct i915_vma *batch;
34ae8455 Chris Wilson 2019-03-01 473 int err = 0, i, v;
34ae8455 Chris Wilson 2019-03-01 474 u32 *cs, *results;
34ae8455 Chris Wilson 2019-03-01 475
34ae8455 Chris Wilson 2019-03-01 476 scratch = create_scratch(ctx);
34ae8455 Chris Wilson 2019-03-01 477 if (IS_ERR(scratch))
34ae8455 Chris Wilson 2019-03-01 478 return PTR_ERR(scratch);
34ae8455 Chris Wilson 2019-03-01 479
34ae8455 Chris Wilson 2019-03-01 480 batch = create_batch(ctx);
34ae8455 Chris Wilson 2019-03-01 481 if (IS_ERR(batch)) {
34ae8455 Chris Wilson 2019-03-01 482 err = PTR_ERR(batch);
34ae8455 Chris Wilson 2019-03-01 483 goto out_scratch;
34ae8455 Chris Wilson 2019-03-01 484 }
34ae8455 Chris Wilson 2019-03-01 485
34ae8455 Chris Wilson 2019-03-01 486 for (i = 0; i < engine->whitelist.count; i++) {
34ae8455 Chris Wilson 2019-03-01 487 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
34ae8455 Chris Wilson 2019-03-01 488 u64 addr = scratch->node.start;
34ae8455 Chris Wilson 2019-03-01 489 struct i915_request *rq;
34ae8455 Chris Wilson 2019-03-01 490 u32 srm, lrm, rsvd;
34ae8455 Chris Wilson 2019-03-01 491 u32 expect;
34ae8455 Chris Wilson 2019-03-01 492 int idx;
34ae8455 Chris Wilson 2019-03-01 493
34ae8455 Chris Wilson 2019-03-01 494 if (wo_register(engine, reg))
34ae8455 Chris Wilson 2019-03-01 495 continue;
34ae8455 Chris Wilson 2019-03-01 496
34ae8455 Chris Wilson 2019-03-01 497 srm = MI_STORE_REGISTER_MEM;
34ae8455 Chris Wilson 2019-03-01 498 lrm = MI_LOAD_REGISTER_MEM;
34ae8455 Chris Wilson 2019-03-01 499 if (INTEL_GEN(ctx->i915) >= 8)
34ae8455 Chris Wilson 2019-03-01 500 lrm++, srm++;
34ae8455 Chris Wilson 2019-03-01 501
34ae8455 Chris Wilson 2019-03-01 502 pr_debug("%s: Writing garbage to %x\n",
34ae8455 Chris Wilson 2019-03-01 503 engine->name, reg);
34ae8455 Chris Wilson 2019-03-01 504
34ae8455 Chris Wilson 2019-03-01 505 cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
34ae8455 Chris Wilson 2019-03-01 506 if (IS_ERR(cs)) {
34ae8455 Chris Wilson 2019-03-01 507 err = PTR_ERR(cs);
34ae8455 Chris Wilson 2019-03-01 508 goto out_batch;
34ae8455 Chris Wilson 2019-03-01 509 }
34ae8455 Chris Wilson 2019-03-01 510
34ae8455 Chris Wilson 2019-03-01 511 /* SRM original */
34ae8455 Chris Wilson 2019-03-01 512 *cs++ = srm;
34ae8455 Chris Wilson 2019-03-01 513 *cs++ = reg;
34ae8455 Chris Wilson 2019-03-01 514 *cs++ = lower_32_bits(addr);
34ae8455 Chris Wilson 2019-03-01 515 *cs++ = upper_32_bits(addr);
34ae8455 Chris Wilson 2019-03-01 516
34ae8455 Chris Wilson 2019-03-01 517 idx = 1;
34ae8455 Chris Wilson 2019-03-01 518 for (v = 0; v < ARRAY_SIZE(values); v++) {
34ae8455 Chris Wilson 2019-03-01 519 /* LRI garbage */
34ae8455 Chris Wilson 2019-03-01 @520 *cs++ = MI_LOAD_REGISTER_IMM(1);
34ae8455 Chris Wilson 2019-03-01 521 *cs++ = reg;
34ae8455 Chris Wilson 2019-03-01 522 *cs++ = values[v];
34ae8455 Chris Wilson 2019-03-01 523
34ae8455 Chris Wilson 2019-03-01 524 /* SRM result */
34ae8455 Chris Wilson 2019-03-01 525 *cs++ = srm;
34ae8455 Chris Wilson 2019-03-01 526 *cs++ = reg;
34ae8455 Chris Wilson 2019-03-01 527 *cs++ = lower_32_bits(addr + sizeof(u32) * idx);
34ae8455 Chris Wilson 2019-03-01 528 *cs++ = upper_32_bits(addr + sizeof(u32) * idx);
34ae8455 Chris Wilson 2019-03-01 529 idx++;
34ae8455 Chris Wilson 2019-03-01 530 }
34ae8455 Chris Wilson 2019-03-01 531 for (v = 0; v < ARRAY_SIZE(values); v++) {
34ae8455 Chris Wilson 2019-03-01 532 /* LRI garbage */
34ae8455 Chris Wilson 2019-03-01 533 *cs++ = MI_LOAD_REGISTER_IMM(1);
34ae8455 Chris Wilson 2019-03-01 534 *cs++ = reg;
34ae8455 Chris Wilson 2019-03-01 535 *cs++ = ~values[v];
34ae8455 Chris Wilson 2019-03-01 536
34ae8455 Chris Wilson 2019-03-01 537 /* SRM result */
34ae8455 Chris Wilson 2019-03-01 538 *cs++ = srm;
34ae8455 Chris Wilson 2019-03-01 539 *cs++ = reg;
34ae8455 Chris Wilson 2019-03-01 540 *cs++ = lower_32_bits(addr + sizeof(u32) * idx);
34ae8455 Chris Wilson 2019-03-01 541 *cs++ = upper_32_bits(addr + sizeof(u32) * idx);
34ae8455 Chris Wilson 2019-03-01 542 idx++;
34ae8455 Chris Wilson 2019-03-01 543 }
34ae8455 Chris Wilson 2019-03-01 544 GEM_BUG_ON(idx * sizeof(u32) > scratch->size);
34ae8455 Chris Wilson 2019-03-01 545
34ae8455 Chris Wilson 2019-03-01 546 /* LRM original -- don't leave garbage in the context! */
34ae8455 Chris Wilson 2019-03-01 547 *cs++ = lrm;
34ae8455 Chris Wilson 2019-03-01 548 *cs++ = reg;
34ae8455 Chris Wilson 2019-03-01 549 *cs++ = lower_32_bits(addr);
34ae8455 Chris Wilson 2019-03-01 550 *cs++ = upper_32_bits(addr);
34ae8455 Chris Wilson 2019-03-01 551
34ae8455 Chris Wilson 2019-03-01 552 *cs++ = MI_BATCH_BUFFER_END;
34ae8455 Chris Wilson 2019-03-01 553
34ae8455 Chris Wilson 2019-03-01 554 i915_gem_object_unpin_map(batch->obj);
34ae8455 Chris Wilson 2019-03-01 555 i915_gem_chipset_flush(ctx->i915);
34ae8455 Chris Wilson 2019-03-01 556
34ae8455 Chris Wilson 2019-03-01 557 rq = i915_request_alloc(engine, ctx);
34ae8455 Chris Wilson 2019-03-01 558 if (IS_ERR(rq)) {
34ae8455 Chris Wilson 2019-03-01 559 err = PTR_ERR(rq);
34ae8455 Chris Wilson 2019-03-01 560 goto out_batch;
34ae8455 Chris Wilson 2019-03-01 561 }
34ae8455 Chris Wilson 2019-03-01 562
34ae8455 Chris Wilson 2019-03-01 563 if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
34ae8455 Chris Wilson 2019-03-01 564 err = engine->emit_init_breadcrumb(rq);
34ae8455 Chris Wilson 2019-03-01 565 if (err)
34ae8455 Chris Wilson 2019-03-01 566 goto err_request;
34ae8455 Chris Wilson 2019-03-01 567 }
34ae8455 Chris Wilson 2019-03-01 568
34ae8455 Chris Wilson 2019-03-01 569 err = engine->emit_bb_start(rq,
34ae8455 Chris Wilson 2019-03-01 570 batch->node.start, PAGE_SIZE,
34ae8455 Chris Wilson 2019-03-01 571 0);
34ae8455 Chris Wilson 2019-03-01 572 if (err)
34ae8455 Chris Wilson 2019-03-01 573 goto err_request;
34ae8455 Chris Wilson 2019-03-01 574
34ae8455 Chris Wilson 2019-03-01 575 err_request:
34ae8455 Chris Wilson 2019-03-01 576 i915_request_add(rq);
34ae8455 Chris Wilson 2019-03-01 577 if (err)
34ae8455 Chris Wilson 2019-03-01 578 goto out_batch;
34ae8455 Chris Wilson 2019-03-01 579
34ae8455 Chris Wilson 2019-03-01 580 if (i915_request_wait(rq, I915_WAIT_LOCKED, HZ / 5) < 0) {
34ae8455 Chris Wilson 2019-03-01 581 pr_err("%s: Futzing %x timedout; cancelling test\n",
34ae8455 Chris Wilson 2019-03-01 582 engine->name, reg);
34ae8455 Chris Wilson 2019-03-01 583 i915_gem_set_wedged(ctx->i915);
34ae8455 Chris Wilson 2019-03-01 584 err = -EIO;
34ae8455 Chris Wilson 2019-03-01 585 goto out_batch;
34ae8455 Chris Wilson 2019-03-01 586 }
34ae8455 Chris Wilson 2019-03-01 587
34ae8455 Chris Wilson 2019-03-01 588 results = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
34ae8455 Chris Wilson 2019-03-01 589 if (IS_ERR(results)) {
34ae8455 Chris Wilson 2019-03-01 590 err = PTR_ERR(results);
34ae8455 Chris Wilson 2019-03-01 591 goto out_batch;
34ae8455 Chris Wilson 2019-03-01 592 }
34ae8455 Chris Wilson 2019-03-01 593
34ae8455 Chris Wilson 2019-03-01 594 GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0xffffffff);
34ae8455 Chris Wilson 2019-03-01 595 rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
34ae8455 Chris Wilson 2019-03-01 596 if (!rsvd) {
34ae8455 Chris Wilson 2019-03-01 597 pr_err("%s: Unable to write to whitelisted register %x\n",
34ae8455 Chris Wilson 2019-03-01 598 engine->name, reg);
34ae8455 Chris Wilson 2019-03-01 599 err = -EINVAL;
34ae8455 Chris Wilson 2019-03-01 600 goto out_unpin;
34ae8455 Chris Wilson 2019-03-01 601 }
34ae8455 Chris Wilson 2019-03-01 602
34ae8455 Chris Wilson 2019-03-01 603 expect = results[0];
34ae8455 Chris Wilson 2019-03-01 604 idx = 1;
34ae8455 Chris Wilson 2019-03-01 605 for (v = 0; v < ARRAY_SIZE(values); v++) {
34ae8455 Chris Wilson 2019-03-01 606 expect = reg_write(expect, values[v], rsvd);
34ae8455 Chris Wilson 2019-03-01 607 if (results[idx] != expect)
34ae8455 Chris Wilson 2019-03-01 608 err++;
34ae8455 Chris Wilson 2019-03-01 609 idx++;
34ae8455 Chris Wilson 2019-03-01 610 }
34ae8455 Chris Wilson 2019-03-01 611 for (v = 0; v < ARRAY_SIZE(values); v++) {
34ae8455 Chris Wilson 2019-03-01 612 expect = reg_write(expect, ~values[v], rsvd);
34ae8455 Chris Wilson 2019-03-01 613 if (results[idx] != expect)
34ae8455 Chris Wilson 2019-03-01 614 err++;
34ae8455 Chris Wilson 2019-03-01 615 idx++;
34ae8455 Chris Wilson 2019-03-01 616 }
34ae8455 Chris Wilson 2019-03-01 617 if (err) {
34ae8455 Chris Wilson 2019-03-01 618 pr_err("%s: %d mismatch between values written to whitelisted register [%x], and values read back!\n",
34ae8455 Chris Wilson 2019-03-01 619 engine->name, err, reg);
34ae8455 Chris Wilson 2019-03-01 620
34ae8455 Chris Wilson 2019-03-01 621 pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
34ae8455 Chris Wilson 2019-03-01 622 engine->name, reg, results[0], rsvd);
34ae8455 Chris Wilson 2019-03-01 623
34ae8455 Chris Wilson 2019-03-01 624 expect = results[0];
34ae8455 Chris Wilson 2019-03-01 625 idx = 1;
34ae8455 Chris Wilson 2019-03-01 626 for (v = 0; v < ARRAY_SIZE(values); v++) {
34ae8455 Chris Wilson 2019-03-01 627 u32 w = values[v];
34ae8455 Chris Wilson 2019-03-01 628
34ae8455 Chris Wilson 2019-03-01 629 expect = reg_write(expect, w, rsvd);
34ae8455 Chris Wilson 2019-03-01 630 pr_info("Wrote %08x, read %08x, expect %08x\n",
34ae8455 Chris Wilson 2019-03-01 631 w, results[idx], expect);
34ae8455 Chris Wilson 2019-03-01 632 idx++;
34ae8455 Chris Wilson 2019-03-01 633 }
34ae8455 Chris Wilson 2019-03-01 634 for (v = 0; v < ARRAY_SIZE(values); v++) {
34ae8455 Chris Wilson 2019-03-01 635 u32 w = ~values[v];
34ae8455 Chris Wilson 2019-03-01 636
34ae8455 Chris Wilson 2019-03-01 637 expect = reg_write(expect, w, rsvd);
34ae8455 Chris Wilson 2019-03-01 638 pr_info("Wrote %08x, read %08x, expect %08x\n",
34ae8455 Chris Wilson 2019-03-01 639 w, results[idx], expect);
34ae8455 Chris Wilson 2019-03-01 640 idx++;
34ae8455 Chris Wilson 2019-03-01 641 }
34ae8455 Chris Wilson 2019-03-01 642
34ae8455 Chris Wilson 2019-03-01 643 err = -EINVAL;
34ae8455 Chris Wilson 2019-03-01 644 }
34ae8455 Chris Wilson 2019-03-01 645 out_unpin:
34ae8455 Chris Wilson 2019-03-01 646 i915_gem_object_unpin_map(scratch->obj);
34ae8455 Chris Wilson 2019-03-01 647 if (err)
34ae8455 Chris Wilson 2019-03-01 648 break;
34ae8455 Chris Wilson 2019-03-01 649 }
34ae8455 Chris Wilson 2019-03-01 650
34ae8455 Chris Wilson 2019-03-01 651 if (igt_flush_test(ctx->i915, I915_WAIT_LOCKED))
34ae8455 Chris Wilson 2019-03-01 652 err = -EIO;
34ae8455 Chris Wilson 2019-03-01 653 out_batch:
34ae8455 Chris Wilson 2019-03-01 654 i915_vma_unpin_and_release(&batch, 0);
34ae8455 Chris Wilson 2019-03-01 655 out_scratch:
34ae8455 Chris Wilson 2019-03-01 656 i915_vma_unpin_and_release(&scratch, 0);
34ae8455 Chris Wilson 2019-03-01 657 return err;
34ae8455 Chris Wilson 2019-03-01 658 }
34ae8455 Chris Wilson 2019-03-01 659
:::::: The code at line 520 was first introduced by commit
:::::: 34ae8455f4d30ddc7c26d914d0f246de37488a99 drm/i915/selftests: Check that whitelisted registers are accessible
:::::: TO: Chris Wilson <chris at chris-wilson.co.uk>
:::::: CC: Chris Wilson <chris at chris-wilson.co.uk>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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