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Eric Anholt:
<blockquote cite="mid:1228408188.19751.11.camel@gaiman.anholt.net"
type="cite">
<pre wrap="">On Thu, 2008-12-04 at 16:58 +0800, Edward Shu wrote:
</pre>
<blockquote type="cite">
<pre wrap="">Hi,
I am investigating a PCI specific issue for Intel DDX drivers.
In i830_driver.c:i830_detect_chipset()
1323 /* Now that we know the chipset, figure
out the resource base addrs */
1324 if (IS_I9XX(pI830)) {
1325 fb_bar = 2;
1326 mmio_bar = 0;
1327 } else {
1328 fb_bar = 0;
1329 mmio_bar = 1;
1330 }
fb_bar is an BAR index in PCI configure space. In G35,
the GMADR spans from 18~1F which can have 64 bit address
in G35. And fb_bar should be 1 instead of 2 following
PCI convention. Why does this wrong fb_bar work by now?
I guess BIOS never give GMADDR a 64bit address so far
tough it has 64bit address ability. However, 64bit address
for GMADR will definitely come. What do you think of this?
</pre>
</blockquote>
<pre wrap=""><!---->
PCI BAR numbers are based on the offset, not the index in the list of
BARs the devie has.
</pre>
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If it is that way, how can it deal with 64bit PCI address? <br>
combining two consecutive BARS together?<br>
<br>
<blockquote cite="mid:1228408188.19751.11.camel@gaiman.anholt.net"
type="cite">
<pre wrap="">
</pre>
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<br>
<pre class="moz-signature" cols="72">--
Best Regards,
Ming.
------------------------------------------
-Edward Shu
-Solaris x86 Engineering, Sun Microsystems
-Blog: <a class="moz-txt-link-freetext" href="http://blogs.sun.com/sming56/">http://blogs.sun.com/sming56/</a>
-tele: +86-10-62673100
__________________________________________
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