<html><head><style type="text/css"></style></head><body><div style="font-family:Courier New,courier,monaco,monospace,sans-serif;font-size:10pt"><div>Hello,<br><br>I have problem with the I2C clock line, on the 9th clock cycle, after the SCL goes down it automatically goes up after 8us. <br><br>I think SCL line should stay low and delay more than 8us, which should be chan->algo.udelay = 20 or whatever what was set in intel_i2c_create().<br><br>In my attached file this the first part of the EDID read (A1,00,FF,FF,FF,FF,FF,FF,00...) on /dev/i2c-2 SDVO-B (GPIO 0x5020).<br><br>Regards,<br>Val<br></div> </div></body></html>