<div class="gmail_quote">On Sat, Jan 14, 2012 at 12:52, Peter Ross <<a href="mailto:pross@xvid.org" target="_blank">pross@xvid.org</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> This patch set enables enables interlaced mode output on the VGA and SDVO connectors of the G35 chipset. History here: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=11220" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=11220</a> I have tested the changes on an ASUS P5E-VM-HDMI mainboard with VGA and HDMI CRTs attached. The G45 and SB documentation suggests that this will also work on those chipsets. (Wording of the vertical timing registers is near identical). Feedback welcome. Peter Ross (2): drm/i915: specify vertical timings in frame units for interlaced modes (gen4+) drm/i915: allow interlaced mode output on the SDVO connector drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 2 files changed, 9 insertions(+), 1 deletions(-) </blockquote><div> I am not very familiar with this area, but both patches look correct to me and are according to the specs as far as I can see. So, for both of them: Reviewed-by: Eugeni Dodonov <<a href="mailto:eugeni.dodonov@intel.com" target="_blank">eugeni.dodonov@intel.com</a>> Thanks! P.S.: it would be interested to gather some Tested-by's for this though.. </div></div> -- Eugeni Dodonov<a href="http://eugeni.dodonov.net/" target="_blank"> </a>