<div class="gmail_quote">On Wed, Jan 18, 2012 at 11:29, Peter Ross <<a href="mailto:pross@xvid.org">pross@xvid.org</a>> wrote: <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> This patch set enables enables interlaced mode output on generation 3 and above chipsets. History here: <a href="https://bugs.freedesktop.org/show_bug.cgi?id=11220" target="_blank">https://bugs.freedesktop.org/show_bug.cgi?id=11220</a> It has been tested on the following hardware: * ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors) * Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector) * Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector) PATCH HISTORY Version 1. Initial cut. Version 2. Set timings for gen3 and ILK/SB chipsets. Allow interlaced output on HDMI connector. Peter Ross (3): drm/i915: specify vertical timings in frame units for interlaced modes (gen3+) drm/i915: allow interlaced mode output on the SDVO connector drm/i915: allow interlaced mode output on the HDMI connector drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ drivers/gpu/drm/i915/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/intel_sdvo.c | 2 +- 3 files changed, 16 insertions(+), 2 deletions(-) </blockquote><div> Everything looks correct to me, thanks for the testing! Reviewed-by: Eugeni Dodonov <<a href="mailto:eugeni.dodonov@intel.com">eugeni.dodonov@intel.com</a>> </div></div> -- Eugeni Dodonov<a href="http://eugeni.dodonov.net/" target="_blank"> </a>