<div dir="ltr">ops, when reworking to let the split as last patch I missed this one...<div style>I'll resend it soon</div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Mar 26, 2013 at 5:05 AM, Daniel Vetter <span dir="ltr"><<a href="mailto:daniel@ffwll.ch" target="_blank">daniel@ffwll.ch</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">On Mon, Mar 25, 2013 at 05:55:52PM -0300, Rodrigo Vivi wrote:<br>
> Power management, in special RC6 enabling, differs across platforms.<br>
> This patch just split out enabling function for HSW.<br>
> This is an attempt to make pm code more clean without multiple IS_HASWELL<br>
> inside enable_rps function. This actually tends to get worse with upcoming<br>
> platforms.<br>
><br>
> Signed-off-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@gmail.com">rodrigo.vivi@gmail.com</a>><br>
<br>
</div>I think the split starts to make sense, but ...<br>
<div class="im"><br>
> ---<br>
>  drivers/gpu/drm/i915/intel_pm.c | 211 +++++++++++++++++++++++++++-------------<br>
>  1 file changed, 146 insertions(+), 65 deletions(-)<br>
><br>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>
> index f6a7366..814846d 100644<br>
> --- a/drivers/gpu/drm/i915/intel_pm.c<br>
> +++ b/drivers/gpu/drm/i915/intel_pm.c<br>
> @@ -2566,13 +2566,9 @@ static void gen6_enable_rps(struct drm_device *dev)<br>
>       /* disable the counters and set deterministic thresholds */<br>
>       I915_WRITE(GEN6_RC_CONTROL, 0);<br>
><br>
> -     if (IS_HASWELL(dev))<br>
> -             I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);<br>
> -     else {<br>
> -             I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);<br>
> -             I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);<br>
> -             I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);<br>
> -     }<br>
<br>
</div>Adding an if block and then again killing it looks strange.<br>
-Daniel<br>
<div><div class="h5"><br>
> +     I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);<br>
> +     I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);<br>
> +     I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);<br>
>       I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);<br>
>       I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);<br>
><br>
> @@ -2580,27 +2576,19 @@ static void gen6_enable_rps(struct drm_device *dev)<br>
>               I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);<br>
><br>
>       I915_WRITE(GEN6_RC_SLEEP, 0);<br>
> -     if (!IS_HASWELL(dev))<br>
> -             I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);<br>
> +     I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);<br>
>       I915_WRITE(GEN6_RC6_THRESHOLD, 50000);<br>
> -     if (!IS_HASWELL(dev)) {<br>
> -             I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);<br>
> -             I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */<br>
> -     }<br>
> +     I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);<br>
> +     I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */<br>
><br>
>       /* Check if we are enabling RC6 */<br>
>       rc6_mode = intel_enable_rc6(dev_priv->dev);<br>
>       if (rc6_mode & INTEL_RC6_ENABLE)<br>
>               rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;<br>
> -<br>
> -     /* We don't use those on Haswell */<br>
> -     if (!IS_HASWELL(dev)) {<br>
> -             if (rc6_mode & INTEL_RC6p_ENABLE)<br>
> -                     rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;<br>
> -<br>
> -             if (rc6_mode & INTEL_RC6pp_ENABLE)<br>
> -                     rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;<br>
> -     }<br>
> +     if (rc6_mode & INTEL_RC6p_ENABLE)<br>
> +             rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;<br>
> +     if (rc6_mode & INTEL_RC6pp_ENABLE)<br>
> +             rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;<br>
><br>
>       DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",<br>
>                       (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",<br>
> @@ -2612,19 +2600,12 @@ static void gen6_enable_rps(struct drm_device *dev)<br>
>                  GEN6_RC_CTL_EI_MODE(1) |<br>
>                  GEN6_RC_CTL_HW_ENABLE);<br>
><br>
> -     if (IS_HASWELL(dev)) {<br>
> -             I915_WRITE(GEN6_RPNSWREQ,<br>
> -                        HSW_FREQUENCY(10));<br>
> -             I915_WRITE(GEN6_RC_VIDEO_FREQ,<br>
> -                        HSW_FREQUENCY(12));<br>
> -     } else {<br>
> -             I915_WRITE(GEN6_RPNSWREQ,<br>
> -                        GEN6_FREQUENCY(10) |<br>
> -                        GEN6_OFFSET(0) |<br>
> -                        GEN6_AGGRESSIVE_TURBO);<br>
> -             I915_WRITE(GEN6_RC_VIDEO_FREQ,<br>
> -                        GEN6_FREQUENCY(12));<br>
> -     }<br>
> +     I915_WRITE(GEN6_RPNSWREQ,<br>
> +                GEN6_FREQUENCY(10) |<br>
> +                GEN6_OFFSET(0) |<br>
> +                GEN6_AGGRESSIVE_TURBO);<br>
> +     I915_WRITE(GEN6_RC_VIDEO_FREQ,<br>
> +                GEN6_FREQUENCY(12));<br>
><br>
>       I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);<br>
>       I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,<br>
> @@ -2643,22 +2624,20 @@ static void gen6_enable_rps(struct drm_device *dev)<br>
>                  GEN6_RP_MEDIA_IS_GFX |<br>
>                  GEN6_RP_ENABLE |<br>
>                  GEN6_RP_UP_BUSY_AVG |<br>
> -                (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));<br>
> -<br>
> -     if (!IS_HASWELL(dev)) {<br>
> -             ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);<br>
> -             if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {<br>
> -                     pcu_mbox = 0;<br>
> -                     ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);<br>
> -                     if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */<br>
> -                             DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max from %dMHz to %dMHz\n",<br>
> -                                              (dev_priv->rps.max_delay & 0xff) * 50,<br>
> -                                              (pcu_mbox & 0xff) * 50);<br>
> -                             dev_priv->rps.max_delay = pcu_mbox & 0xff;<br>
> -                     }<br>
> -             } else {<br>
> -                     DRM_DEBUG_DRIVER("Failed to set the min frequency\n");<br>
> +                GEN6_RP_DOWN_IDLE_CONT);<br>
> +<br>
> +     ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);<br>
> +     if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {<br>
> +             pcu_mbox = 0;<br>
> +             ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);<br>
> +             if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */<br>
> +                     DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max from %dMHz to %dMHz\n",<br>
> +                                      (dev_priv->rps.max_delay & 0xff) * 50,<br>
> +                                      (pcu_mbox & 0xff) * 50);<br>
> +                     dev_priv->rps.max_delay = pcu_mbox & 0xff;<br>
>               }<br>
> +     } else {<br>
> +             DRM_DEBUG_DRIVER("Failed to set the min frequency\n");<br>
>       }<br>
><br>
>       gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);<br>
> @@ -2672,25 +2651,124 @@ static void gen6_enable_rps(struct drm_device *dev)<br>
>       /* enable all PM interrupts */<br>
>       I915_WRITE(GEN6_PMINTRMSK, 0);<br>
><br>
> -     if (!IS_HASWELL(dev)) {<br>
> -             rc6vids = 0;<br>
> -             ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);<br>
> -             if (IS_GEN6(dev) && ret) {<br>
> -                     DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");<br>
> -             } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {<br>
> -                     DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",<br>
> -                                      GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);<br>
> -                     rc6vids &= 0xffff00;<br>
> -                     rc6vids |= GEN6_ENCODE_RC6_VID(450);<br>
> -                     ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);<br>
> -                     if (ret)<br>
> -                             DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");<br>
> -             }<br>
> +     rc6vids = 0;<br>
> +     ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);<br>
> +     if (IS_GEN6(dev) && ret) {<br>
> +             DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");<br>
> +     } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {<br>
> +             DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",<br>
> +                       GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);<br>
> +             rc6vids &= 0xffff00;<br>
> +             rc6vids |= GEN6_ENCODE_RC6_VID(450);<br>
> +             ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);<br>
> +             if (ret)<br>
> +                     DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");<br>
>       }<br>
><br>
>       gen6_gt_force_wake_put(dev_priv);<br>
>  }<br>
><br>
> +static void hsw_enable_rps(struct drm_device *dev)<br>
> +{<br>
> +     struct drm_i915_private *dev_priv = dev->dev_private;<br>
> +     struct intel_ring_buffer *ring;<br>
> +     u32 rp_state_cap;<br>
> +     u32 gt_perf_status;<br>
> +     u32 rc6_mask = 0;<br>
> +     u32 gtfifodbg;<br>
> +     int rc6_mode;<br>
> +     int i;<br>
> +<br>
> +     WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));<br>
> +<br>
> +     /* Here begins a magic sequence of register writes to enable<br>
> +      * auto-downclocking.<br>
> +      *<br>
> +      * Perhaps there might be some value in exposing these to<br>
> +      * userspace...<br>
> +      */<br>
> +     I915_WRITE(GEN6_RC_STATE, 0);<br>
> +<br>
> +     /* Clear the DBG now so we don't confuse earlier errors */<br>
> +     if ((gtfifodbg = I915_READ(GTFIFODBG))) {<br>
> +             DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);<br>
> +             I915_WRITE(GTFIFODBG, gtfifodbg);<br>
> +     }<br>
> +<br>
> +     gen6_gt_force_wake_get(dev_priv);<br>
> +<br>
> +     rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);<br>
> +     gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);<br>
> +<br>
> +     /* In units of 100MHz */<br>
> +     dev_priv->rps.max_delay = rp_state_cap & 0xff;<br>
> +     dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;<br>
> +     dev_priv->rps.cur_delay = 0;<br>
> +<br>
> +     /* disable the counters and set deterministic thresholds */<br>
> +     I915_WRITE(GEN6_RC_CONTROL, 0);<br>
> +<br>
> +     I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);<br>
> +     I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);<br>
> +     I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);<br>
> +<br>
> +     for_each_ring(ring, dev_priv, i)<br>
> +             I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);<br>
> +<br>
> +     I915_WRITE(GEN6_RC_SLEEP, 0);<br>
> +     I915_WRITE(GEN6_RC6_THRESHOLD, 50000);<br>
> +<br>
> +     /* Check if we are enabling RC6 */<br>
> +     rc6_mode = intel_enable_rc6(dev_priv->dev);<br>
> +     if (rc6_mode & INTEL_RC6_ENABLE)<br>
> +             rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;<br>
> +<br>
> +     DRM_INFO("Enabling RC6 states: RC6 %s\n",<br>
> +                     (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");<br>
> +<br>
> +     I915_WRITE(GEN6_RC_CONTROL,<br>
> +                rc6_mask |<br>
> +                GEN6_RC_CTL_EI_MODE(1) |<br>
> +                GEN6_RC_CTL_HW_ENABLE);<br>
> +<br>
> +     I915_WRITE(GEN6_RPNSWREQ,<br>
> +                HSW_FREQUENCY(10));<br>
> +     I915_WRITE(GEN6_RC_VIDEO_FREQ,<br>
> +                HSW_FREQUENCY(12));<br>
> +<br>
> +     I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);<br>
> +     I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,<br>
> +                dev_priv->rps.max_delay << 24 |<br>
> +                dev_priv->rps.min_delay << 16);<br>
> +<br>
> +     I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);<br>
> +     I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);<br>
> +     I915_WRITE(GEN6_RP_UP_EI, 66000);<br>
> +     I915_WRITE(GEN6_RP_DOWN_EI, 350000);<br>
> +<br>
> +     I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);<br>
> +     I915_WRITE(GEN6_RP_CONTROL,<br>
> +                GEN6_RP_MEDIA_TURBO |<br>
> +                GEN6_RP_MEDIA_HW_NORMAL_MODE |<br>
> +                GEN6_RP_MEDIA_IS_GFX |<br>
> +                GEN6_RP_ENABLE |<br>
> +                GEN6_RP_UP_BUSY_AVG |<br>
> +                GEN7_RP_DOWN_IDLE_AVG);<br>
> +<br>
> +     gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);<br>
> +<br>
> +     /* requires MSI enabled */<br>
> +     I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);<br>
> +     spin_lock_irq(&dev_priv->rps.lock);<br>
> +     WARN_ON(dev_priv->rps.pm_iir != 0);<br>
> +     I915_WRITE(GEN6_PMIMR, 0);<br>
> +     spin_unlock_irq(&dev_priv->rps.lock);<br>
> +     /* enable all PM interrupts */<br>
> +     I915_WRITE(GEN6_PMINTRMSK, 0);<br>
> +<br>
> +     gen6_gt_force_wake_put(dev_priv);<br>
> +}<br>
> +<br>
>  static void gen6_update_ring_freq(struct drm_device *dev)<br>
>  {<br>
>       struct drm_i915_private *dev_priv = dev->dev_private;<br>
> @@ -3480,7 +3558,10 @@ static void intel_gen6_powersave_work(struct work_struct *work)<br>
>       struct drm_device *dev = dev_priv->dev;<br>
><br>
>       mutex_lock(&dev_priv->rps.hw_lock);<br>
> -     gen6_enable_rps(dev);<br>
> +     if (IS_HASWELL(dev))<br>
> +             hsw_enable_rps(dev);<br>
> +     else<br>
> +             gen6_enable_rps(dev);<br>
>       gen6_update_ring_freq(dev);<br>
>       mutex_unlock(&dev_priv->rps.hw_lock);<br>
>  }<br>
> --<br>
> 1.8.1.4<br>
><br>
</div></div>> _______________________________________________<br>
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> <a href="mailto:Intel-gfx@lists.freedesktop.org">Intel-gfx@lists.freedesktop.org</a><br>
> <a href="http://lists.freedesktop.org/mailman/listinfo/intel-gfx" target="_blank">http://lists.freedesktop.org/mailman/listinfo/intel-gfx</a><br>
<span class="HOEnZb"><font color="#888888"><br>
--<br>
Daniel Vetter<br>
Software Engineer, Intel Corporation<br>
<a href="tel:%2B41%20%280%29%2079%20365%2057%2048" value="+41793655748">+41 (0) 79 365 57 48</a> - <a href="http://blog.ffwll.ch" target="_blank">http://blog.ffwll.ch</a><br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div>