<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Apr 9, 2013 at 5:37 AM, Ville Syrjälä <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="im">On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote:<br>
> Display register 46500h bit 23 must be set to 1b for the entire time that<br>
> Frame Buffer Compression is enabled.<br>
<br>
</div>So should we enable it again after FBC is disabled to avoid wasting<br>
power?<br></blockquote><div><br></div><div style>I didn't take the opposite direction because it wasn't explicit.</div><div style>I tested to enabled it again after FBC is disabled but I didn't see any difference.</div>
<div style>So, you suggestion is to enable back anyway?</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
><br>
> Signed-off-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@gmail.com">rodrigo.vivi@gmail.com</a>><br>
> ---<br>
>  drivers/gpu/drm/i915/i915_reg.h | 3 +++<br>
>  drivers/gpu/drm/i915/intel_pm.c | 2 ++<br>
>  2 files changed, 5 insertions(+)<br>
><br>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h<br>
> index 2340bc2..2ef0292 100644<br>
> --- a/drivers/gpu/drm/i915/i915_reg.h<br>
> +++ b/drivers/gpu/drm/i915/i915_reg.h<br>
> @@ -863,6 +863,9 @@<br>
>                                            _HSW_PIPE_SLICE_CHICKEN_1_A, + \<br>
>                                            _HSW_PIPE_SLICE_CHICKEN_1_B)<br>
><br>
> +#define HSW_CLKGATE_DISABLE_PART_1   0x46500<br>
> +#define   HSW_DPFC_GATING_DISABLE    (1<<23)<br>
> +<br>
>  /*<br>
>   * GPIO regs<br>
>   */<br>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>
> index 0628a84..f2ce541 100644<br>
> --- a/drivers/gpu/drm/i915/intel_pm.c<br>
> +++ b/drivers/gpu/drm/i915/intel_pm.c<br>
> @@ -281,6 +281,8 @@ static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval)<br>
>       /* WaFbcAsynchFlipDisableFbcQueue */<br>
>       I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),<br>
>                  HSW_BYPASS_FBC_QUEUE);<br>
> +     /* WaFbcDisableDpfcClockGating */<br>
> +     I915_WRITE(HSW_CLKGATE_DISABLE_PART_1, HSW_DPFC_GATING_DISABLE);<br>
><br>
>       if (obj->fence_reg != I915_FENCE_REG_NONE) {<br>
>               I915_WRITE(SNB_DPFC_CTL_SA,<br>
> --<br>
> 1.8.1.4<br>
><br>
</div></div>> _______________________________________________<br>
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<span class="HOEnZb"><font color="#888888"><br>
--<br>
Ville Syrjälä<br>
Intel OTC<br>
</font></span></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div></div>