<div dir="ltr"><br><div class="gmail_extra"><br><br><div class="gmail_quote">On Tue, Apr 16, 2013 at 2:49 PM, Ville Syrjälä <span dir="ltr"><<a href="mailto:ville.syrjala@linux.intel.com" target="_blank">ville.syrjala@linux.intel.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5">On Tue, Apr 16, 2013 at 01:33:44PM -0300, Rodrigo Vivi wrote:<br>
> This patch introduce Frame Buffer Compression (FBC) support for HSW.<br>
> It adds a new function haswell_enable_fbc to avoid getting<br>
> ironlake_enable_fbc messed with many IS_HASWELL checks.<br>
><br>
> v2: Fixes from Ville.<br>
> * Fix Plane. FBC is tied to primary plane A in HSW<br>
> * Fix DPFC initial write to avoid let trash on the register.<br>
><br>
> v3: Checking for bad plane on intel_update_fbc() as Chris suggested.<br>
><br>
> v4: Ville pointed out that according to BSpec FBC_CTL bits 0:3 must be 0.<br>
><br>
> Cc: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>><br>
> Cc: Ville Syrjälä <<a href="mailto:ville.syrjala@linux.intel.com">ville.syrjala@linux.intel.com</a>><br>
> Signed-off-by: Rodrigo Vivi <<a href="mailto:rodrigo.vivi@gmail.com">rodrigo.vivi@gmail.com</a>><br>
> ---<br>
> drivers/gpu/drm/i915/i915_drv.c | 1 +<br>
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++<br>
> drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++++++++++++++++++++++++++++++++--<br>
> 3 files changed, 47 insertions(+), 2 deletions(-)<br>
><br>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c<br>
> index 9ebe895..ba0935d 100644<br>
> --- a/drivers/gpu/drm/i915/i915_drv.c<br>
> +++ b/drivers/gpu/drm/i915/i915_drv.c<br>
> @@ -314,6 +314,7 @@ static const struct intel_device_info intel_haswell_m_info = {<br>
> GEN7_FEATURES,<br>
> .is_haswell = 1,<br>
> .is_mobile = 1,<br>
> + .has_fbc = 1,<br>
> };<br>
><br>
> static const struct pci_device_id pciidlist[] = { /* aka */<br>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h<br>
> index 077d40f..b9725ba 100644<br>
> --- a/drivers/gpu/drm/i915/i915_reg.h<br>
> +++ b/drivers/gpu/drm/i915/i915_reg.h<br>
> @@ -857,6 +857,12 @@<br>
> #define SNB_CPU_FENCE_ENABLE (1<<29)<br>
> #define DPFC_CPU_FENCE_OFFSET 0x100104<br>
><br>
> +/* Framebuffer compression for Haswell */<br>
> +#define HSW_FBC_RT_BASE 0x7020<br>
> +#define HSW_FBC_RT_BASE_ADDR_SHIFT 12<br>
> +<br>
> +#define HSW_DPFC_CTL_FENCE_EN (1<<28)<br>
> +#define HSW_DPFC_CTL_DISABLE_SLB_INIT (1<<15)<br>
<br>
</div></div>These registers/bits already exists on IVB. All the registers you set<br>
seem to be in line with IVB BSpec, so I think you just need to to<br>
s/haswell/gen7/ everywhere, and then we get FBC for IVB for free.<br>
<br>
Well, the only real work left would be adding plane B and C FBC<br>
support on IVB.<br></blockquote><div><br></div><div style>I implemented here the ivb version, tested and it didn't worked.</div><div style>So I believe we can go on with HSW names and change it in the future if we can really get fbc working on ivb.</div>
<div style>What do you think?</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
The new DPFC_CTL bits should also probably be grouped with the rest of<br>
the ILK_DPFC_CONTROL bits, otherwise it's difficult to know which<br>
register they belong to.<br></blockquote><div><br></div><div style>I just didn't do this because it was already organized by platforms. But it makes sense. coming on v5.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div><div class="h5"><br>
><br>
> /*<br>
> * GPIO regs<br>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>
> index f747cb0..7b20fc5 100644<br>
> --- a/drivers/gpu/drm/i915/intel_pm.c<br>
> +++ b/drivers/gpu/drm/i915/intel_pm.c<br>
> @@ -253,6 +253,38 @@ static bool ironlake_fbc_enabled(struct drm_device *dev)<br>
> return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;<br>
> }<br>
><br>
> +static void haswell_enable_fbc(struct drm_crtc *crtc, unsigned long interval)<br>
> +{<br>
> + struct drm_device *dev = crtc->dev;<br>
> + struct drm_i915_private *dev_priv = dev->dev_private;<br>
> + struct drm_framebuffer *fb = crtc->fb;<br>
> + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);<br>
> + struct drm_i915_gem_object *obj = intel_fb->obj;<br>
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);<br>
> + unsigned long stall_watermark = 200;<br>
> +<br>
> + I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |<br>
> + (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |<br>
> + (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));<br>
> + I915_WRITE(HSW_FBC_RT_BASE,<br>
> + obj->gtt_offset << HSW_FBC_RT_BASE_ADDR_SHIFT |<br>
> + ILK_FBC_RT_VALID);<br>
> +<br>
> + I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |<br>
> + HSW_DPFC_CTL_FENCE_EN | HSW_DPFC_CTL_DISABLE_SLB_INIT);<br>
> +<br>
> + if (obj->fence_reg != I915_FENCE_REG_NONE) {<br>
<br>
</div></div>Is there actually a case that we wouldn't have a fence? I think we<br>
always reserve a fence for scanout even though we wouldn't really<br>
need it on gen4+ (or for untiled on gen2-3). At least we don't have any<br>
sanity checks for fence_reg in the ironlake_enable_fbc().<br></blockquote><div style><br></div><div style>Yeah, you are right. I don't see any case without the fence. So I'm going to remove this check and else block in v5.</div>
<div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
But if this can happen, then shouldn't we also clear the<br>
"fence enable" bit from ILK_DPFC_CONTROL? </blockquote><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="HOEnZb"><div class="h5"><br>
> + I915_WRITE(SNB_DPFC_CTL_SA,<br>
> + SNB_CPU_FENCE_ENABLE | obj->fence_reg);<br>
> + I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);<br>
> + } else<br>
> + I915_WRITE(SNB_DPFC_CTL_SA, ~SNB_CPU_FENCE_ENABLE);<br>
> +<br>
> + sandybridge_blit_fbc_update(dev);<br>
> +<br>
> + DRM_DEBUG_KMS("enabled fbc on plane A\n");<br>
> +}<br>
> +<br>
> bool intel_fbc_enabled(struct drm_device *dev)<br>
> {<br>
> struct drm_i915_private *dev_priv = dev->dev_private;<br>
> @@ -460,7 +492,8 @@ void intel_update_fbc(struct drm_device *dev)<br>
> dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;<br>
> goto out_disable;<br>
> }<br>
> - if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {<br>
> + if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev))<br>
> + && intel_crtc->plane != 0) {<br>
> DRM_DEBUG_KMS("plane not 0, disabling compression\n");<br>
> dev_priv->no_fbc_reason = FBC_BAD_PLANE;<br>
> goto out_disable;<br>
> @@ -4180,7 +4213,12 @@ void intel_init_pm(struct drm_device *dev)<br>
> if (I915_HAS_FBC(dev)) {<br>
> if (HAS_PCH_SPLIT(dev)) {<br>
> dev_priv->display.fbc_enabled = ironlake_fbc_enabled;<br>
> - dev_priv->display.enable_fbc = ironlake_enable_fbc;<br>
> + if (IS_HASWELL(dev))<br>
> + dev_priv->display.enable_fbc =<br>
> + haswell_enable_fbc;<br>
> + else<br>
> + dev_priv->display.enable_fbc =<br>
> + ironlake_enable_fbc;<br>
> dev_priv->display.disable_fbc = ironlake_disable_fbc;<br>
> } else if (IS_GM45(dev)) {<br>
> dev_priv->display.fbc_enabled = g4x_fbc_enabled;<br>
> --<br>
> 1.8.1.4<br>
<br>
</div></div><div class="HOEnZb"><div class="h5">--<br>
Ville Syrjälä<br>
Intel OTC<br>
</div></div></blockquote></div><br><br clear="all"><div><br></div>-- <br><div>Rodrigo Vivi</div><div>Blog: <a href="http://blog.vivi.eng.br" target="_blank">http://blog.vivi.eng.br</a></div><div> </div>
</div></div>