<html><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8"></head><body ><div>Ouch good catch. I'll put the cancelation outside the scope of the lock. </div><div><br></div><div><br></div>--<div>Jesse Barnes, Intel Open Source Technology Center</div> <br><br><br>-------- Original message --------<br>From: Daniel Vetter <daniel@ffwll.ch> <br>Date: 04/22/2013 11:52 AM (GMT-08:00) <br>To: Jesse Barnes <jbarnes@virtuousgeek.org> <br>Cc: intel-gfx <intel-gfx@lists.freedesktop.org> <br>Subject: Re: [Intel-gfx] [PATCH] drm/i915: make sure GPU freq drops to minimum
after entering RC6 v2 <br> <br><br>On Mon, Apr 22, 2013 at 7:54 PM, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:<br>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>> index 2557926..4669d8c 100644<br>> --- a/drivers/gpu/drm/i915/intel_pm.c<br>> +++ b/drivers/gpu/drm/i915/intel_pm.c<br>> @@ -2545,6 +2545,9 @@ static void gen6_disable_rps(struct drm_device *dev)<br>> spin_unlock_irq(&dev_priv->rps.lock);<br>><br>> I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));<br>> +<br>> + if (IS_VALLEYVIEW(dev))<br>> + cancel_delayed_work_sync(&dev_priv->rps.vlv_work);<br><br>We hold the rps mutex here, so this can deadlock.<br>-Daniel<br>--<br>Daniel Vetter<br>Software Engineer, Intel Corporation<br>+41 (0) 79 365 57 48 - http://blog.ffwll.ch<br><br></body>