<div dir="ltr">Is there some reason why this is a difficult change to evaluate?</div><div class="gmail_extra"><br><br><div class="gmail_quote">On Mon, Jul 8, 2013 at 11:52 AM, Stuart Abercrombie <span dir="ltr"><<a href="mailto:sabercrombie@google.com" target="_blank">sabercrombie@google.com</a>></span> wrote:<br> <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">So, what's the conclusion?</div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><br> <div class="gmail_quote">On Mon, Jun 24, 2013 at 4:28 PM, Stuart Abercrombie <span dir="ltr"><<a href="mailto:sabercrombie@google.com" target="_blank">sabercrombie@google.com</a>></span> wrote:<br> <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">This is with the patch.</div><div><div><div class="gmail_extra"><br><br><div class="gmail_quote"> On Sun, Jun 23, 2013 at 11:59 PM, Daniel Vetter <span dir="ltr"><<a href="mailto:daniel@ffwll.ch" target="_blank">daniel@ffwll.ch</a>></span> wrote:<br> <blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div>On Sat, Jun 22, 2013 at 12:52 AM, Stuart Abercrombie<br> <<a href="mailto:sabercrombie@google.com" target="_blank">sabercrombie@google.com</a>> wrote:<br> > Maybe I missed something, but I didn't see a response to this. Can we get<br> > this fix in?<br> <br> </div>Sorry for the delay, I've lost track of this. Can you please boot with<br> drm.debug=0xe and attach the full dmesg (with or without your patch)?<br> <span><font color="#888888">-Daniel<br> </font></span><div><div><br> ><br> ><br> > On Wed, May 29, 2013 at 9:22 AM, Stuart Abercrombie<br> > <<a href="mailto:sabercrombie@google.com" target="_blank">sabercrombie@google.com</a>> wrote:<br> >><br> >> Without this change I saw PIPE_FIFO_UNDERRUN_STATUS set in PIPEASTAT,<br> >> which I took to indicate an underrun problem.<br> >><br> >> Here's what I found with other modes on this monitor:<br> >><br> >> 1920x1200 works with pixel doubling enabled. Pixel clock 193.2 MHz.<br> >> 2048x1152 works with pixel doubling enabled. Pixel clock 198.0 MHz.<br> >> 1600x1200 works with pixel doubling disabled. Pixel clock 162.0 MHz.<br> >> 2048x1280 fails with pixel doubling disabled. PIxel clock 174.2 MHz..<br> >><br> >> Based on this, it seems the threshold needs to be be between 162.0MHz and<br> >> 174.2MHz, whereas currently it's at 180MHz. The change puts it at 170MHz.<br> >><br> >> Stuart<br> >><br> >><br> >> On Wed, May 29, 2013 at 8:22 AM, Daniel Vetter <<a href="mailto:daniel@ffwll.ch" target="_blank">daniel@ffwll.ch</a>> wrote:<br> >>><br> >>> On Tue, May 28, 2013 at 10:39:07AM -0700, Stuart Abercrombie wrote:<br> >>> > Any comments?<br> >>> ><br> >>> > Without this, plugging one of the older Chromebook models into a Dell<br> >>> > U3011<br> >>> > monitor produces a garbled display at the default 2048x1280 resolution.<br> >>> ><br> >>> > The original threshold was apparently fairly arbitrary:<br> >>> ><br> >>> ><br> >>> > <a href="http://cgit.freedesktop.org/~anholt/xf86-video-intel/commit/?id=8fcf9a81179ee8577ddab5e904c58fbfd14cf59c" target="_blank">http://cgit.freedesktop.org/~anholt/xf86-video-intel/commit/?id=8fcf9a81179ee8577ddab5e904c58fbfd14cf59c</a><br> >>><br> >>> Do you see any pipe underruns without this patch? There are some not-yet<br> >>> implemented tricks we should be pulling around re-splitting DSP_ARB fifo<br> >>> entries, which tend to totally kill high-res modes.<br> >>> -Daniel<br> >>><br> >>> > .<br> >>> ><br> >>> > Stuart<br> >>> ><br> >>> ><br> >>> > On Mon, May 20, 2013 at 11:15 AM, Stuart Abercrombie <<br> >>> > <a href="mailto:sabercrombie@chromium.org" target="_blank">sabercrombie@chromium.org</a>> wrote:<br> >>> ><br> >>> > > 90% of core speed (=180MHz dot clock) is too high for 2048x1280 to<br> >>> > > get<br> >>> > > pixel doubling on Pineview, which it needs to avoid underruns, so<br> >>> > > lower this to 85%.<br> >>> > ><br> >>> > > Signed-off-by: Stuart Abercrombie <<a href="mailto:sabercrombie@chromium.org" target="_blank">sabercrombie@chromium.org</a>><br> >>> > > ---<br> >>> > > drivers/gpu/drm/i915/intel_display.c | 4 ++--<br> >>> > > 1 file changed, 2 insertions(+), 2 deletions(-)<br> >>> > ><br> >>> > > diff --git a/drivers/gpu/drm/i915/intel_display.c<br> >>> > > b/drivers/gpu/drm/i915/intel_display.c<br> >>> > > index efe8299..9c924e9 100644<br> >>> > > --- a/drivers/gpu/drm/i915/intel_display.c<br> >>> > > +++ b/drivers/gpu/drm/i915/intel_display.c<br> >>> > > @@ -4564,14 +4564,14 @@ static void i9xx_set_pipeconf(struct<br> >>> > > intel_crtc<br> >>> > > *intel_crtc)<br> >>> > > pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));<br> >>> > ><br> >>> > > if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {<br> >>> > > - /* Enable pixel doubling when the dot clock is > 90%<br> >>> > > of<br> >>> > > the (display)<br> >>> > > + /* Enable pixel doubling when the dot clock is > 85%<br> >>> > > of<br> >>> > > the (display)<br> >>> > > * core speed.<br> >>> > > *<br> >>> > > * XXX: No double-wide on 915GM pipe B. Is that the<br> >>> > > only<br> >>> > > reason for the<br> >>> > > * pipe == 0 check?<br> >>> > > */<br> >>> > > if (intel_crtc->config.requested_mode.clock ><br> >>> > > - dev_priv->display.get_display_clock_speed(dev) *<br> >>> > > 9 /<br> >>> > > 10)<br> >>> > > + dev_priv->display.get_display_clock_speed(dev) *<br> >>> > > 17 /<br> >>> > > 20)<br> >>> > > pipeconf |= PIPECONF_DOUBLE_WIDE;<br> >>> > > else<br> >>> > > pipeconf &= ~PIPECONF_DOUBLE_WIDE;<br> >>> > > --<br> >>> > > 1.8.2.1<br> >>> > ><br> >>> > ><br> >>><br> >>> > _______________________________________________<br> >>> > Intel-gfx mailing list<br> >>> > <a href="mailto:Intel-gfx@lists.freedesktop.org" target="_blank">Intel-gfx@lists.freedesktop.org</a><br> >>> > <a href="http://lists.freedesktop.org/mailman/listinfo/intel-gfx" target="_blank">http://lists.freedesktop.org/mailman/listinfo/intel-gfx</a><br> >>><br> >>><br> >>> --<br> >>> Daniel Vetter<br> >>> Software Engineer, Intel Corporation<br> >>> <a href="tel:%2B41%20%280%29%2079%20365%2057%2048" value="+41793655748" target="_blank">+41 (0) 79 365 57 48</a> - <a href="http://blog.ffwll.ch" target="_blank">http://blog.ffwll.ch</a><br> >><br> >><br> ><br> <br> <br> <br> --<br> Daniel Vetter<br> Software Engineer, Intel Corporation<br> <a href="tel:%2B41%20%280%29%2079%20365%2057%2048" value="+41793655748" target="_blank">+41 (0) 79 365 57 48</a> - <a href="http://blog.ffwll.ch" target="_blank">http://blog.ffwll.ch</a><br> </div></div></blockquote></div><br></div> </div></div></blockquote></div><br></div> </div></div></blockquote></div><br></div>