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<p class="MsoPlainText"><span lang="EN-US">Hi Jesse,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> When updated your patches(drm/i915: "Scotty, I need more power!"), I found that latest kernel source changed much and can't patch successfully.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">e.g. <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> This is the kernel source drivers/gpu/drm/i915/intel_pm.c in (drm-intel-next-queued) git-3b27af3:
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3331 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3332 }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3333<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3334 <b>gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);</b><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3335<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3336 gen6_enable_rps_interrupts(dev);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3337<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3338 rc6vids = 0;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">3339 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">But in the patch:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">--- a/drivers/gpu/drm/i915/intel_pm.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">+++ b/drivers/gpu/drm/i915/intel_pm.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">@@ -3323,19 +3323,25 @@ static void gen6_enable_rps(struct drm_device *dev)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> DRM_DEBUG_DRIVER("Failed to set the min frequency\n");<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"> }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- <b>gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);</b><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">-<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- /* requires MSI enabled */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- spin_lock_irq(&dev_priv->rps.lock);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- /* FIXME: Our interrupt enabling sequence is bonghits.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- * dev_priv->rps.pm_iir really should be 0 here. */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">- dev_priv->rps.pm_iir = 0;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Could you give us new patch that based on latest kernel?
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Thanks,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Meng<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">-----Original Message-----<br>
From: Jesse Barnes [mailto:jbarnes@virtuousgeek.org] <br>
Sent: Saturday, July 27, 2013 6:33 AM<br>
To: Chris Wilson<br>
Cc: intel-gfx@lists.freedesktop.org; Zhang, Ouping; Meng, Mengmeng<br>
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Adjustable Render Power State policies</span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Cool... I'd like to see if Ouping and Mengmeng can work together to get power & power numbers across a bunch of workloads for these policies.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Ouping & Mengmeng, can you run your usual battery of stuff against each of these settings and report back the results?<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Thanks,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Jesse<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">On Fri, 26 Jul 2013 23:24:11 +0100<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk"><span style="color:windowtext;text-decoration:none">chris@chris-wilson.co.uk</span></a>> wrote:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> As a complement to the suggestions put forward by Jesse in<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> drm/i915: "Scotty, I need more power!"<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> (<a href="mailto:1372436290-3297-1-git-send-email-jbarnes@virtuousgeek.org"><span style="color:windowtext;text-decoration:none">1372436290-3297-1-git-send-email-jbarnes@virtuousgeek.org</span></a>)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> and<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> drm/i915: boost GPU and CPU freq when leaving idle<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> (<a href="mailto:1372438472-3233-1-git-send-email-jbarnes@virtuousgeek.org"><span style="color:windowtext;text-decoration:none">1372438472-3233-1-git-send-email-jbarnes@virtuousgeek.org</span></a>)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> we also have the ability to fine tune how we respond to the GPU's
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> requests for more power.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> This patch introduces the i915.rps_policy module parameter that
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> adjusts how we respond to the upclock request:<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> 1 - Powersaving (current implementation)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> Increase the frequency by one bin on every upclock request.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> 2 - Conservative (new default)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> When waking from idle, boost the render frequency to the<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> default render frequency (RP1)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> 3 - Ondemand<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> At every upclock request, increase to halfway between the current<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> frequency and maximum. This should give rapid upclocking similar<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> to tcp window scaling.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> 4 - Performance<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> Every time the GPU wants more power, give it everything we have.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk"><span style="color:windowtext;text-decoration:none">chris@chris-wilson.co.uk</span></a>><o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> ---<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> drivers/gpu/drm/i915/i915_drv.c | 8 +++++++
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> drivers/gpu/drm/i915/i915_drv.h | 2 ++
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> drivers/gpu/drm/i915/i915_irq.c | 46
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +++++++++++++++++++++++++++++------------<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> drivers/gpu/drm/i915/intel_pm.c | 1 +<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> 4 files changed, 44 insertions(+), 13 deletions(-)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> diff --git a/drivers/gpu/drm/i915/i915_drv.c
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> b/drivers/gpu/drm/i915/i915_drv.c index 1d8cedc..7ad80f4 100644<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> --- a/drivers/gpu/drm/i915/i915_drv.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +++ b/drivers/gpu/drm/i915/i915_drv.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> @@ -72,6 +72,14 @@ MODULE_PARM_DESC(i915_enable_rc6,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> "default: -1 (use per-chip default)");<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +int i915_rps_policy __read_mostly = 1; module_param_named(rps_policy,
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +i915_rps_policy, int, 0600); MODULE_PARM_DESC(rps_policy,<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + "Specify a policy to use to respond to requests to change the render clock. "<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + "Different levels of uplocking agressiveness can be selected"<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + "(0 = Powersaving, slowly uplock; 1 = Conservative, when the gpu wakes from idle go straight to RP1/RPe (recommended minimum active GPU frequency); 2 = Ondemand, rapidly increase frequency whilst upclocking;
4 = Performance, always upclock to maximum frequency). "<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + "default: 1 (Conservative)");<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> int i915_enable_fbc __read_mostly = -1;
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> MODULE_PARM_DESC(i915_enable_fbc, diff --git
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> index ec14124..71232bc 100644<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> --- a/drivers/gpu/drm/i915/i915_drv.h<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +++ b/drivers/gpu/drm/i915/i915_drv.h<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> @@ -811,6 +811,7 @@ struct intel_gen6_power_mgmt {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> u8 min_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> u8 max_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> u8 rpe_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + u8 rp1_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> u8 hw_max;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> struct delayed_work delayed_resume_work; @@ -1635,6 +1636,7 @@
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> extern int i915_lvds_channel_mode __read_mostly; extern int
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> i915_panel_use_ssc __read_mostly; extern int i915_vbt_sdvo_panel_type
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> __read_mostly; extern int i915_enable_rc6 __read_mostly;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +extern int i915_rps_policy __read_mostly;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> extern int i915_enable_fbc __read_mostly; extern bool
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> i915_enable_hangcheck __read_mostly; extern int i915_enable_ppgtt
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> __read_mostly; diff --git a/drivers/gpu/drm/i915/i915_irq.c
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> b/drivers/gpu/drm/i915/i915_irq.c index ee3e49c..edd73c0 100644<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> --- a/drivers/gpu/drm/i915/i915_irq.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +++ b/drivers/gpu/drm/i915/i915_irq.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> @@ -728,14 +728,32 @@ static void gen6_pm_rps_work(struct work_struct *work)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> mutex_lock(&dev_priv->rps.hw_lock);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - new_delay = dev_priv->rps.cur_delay + 1;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + switch (i915_rps_policy) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + case 0: /* Powersave, slow increase in frequency */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.cur_delay + 1;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + break;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + case 1: /* Conservative, jump directly to RPe */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.rp1_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + if (dev_priv->rps.cur_delay >= new_delay)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.cur_delay + 1;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + break;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + case 2: /* Ondemand, halfway to maximum */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.cur_delay + 1;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + if (new_delay < dev_priv->rps.rp1_delay)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.rp1_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + else<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = (dev_priv->rps.max_delay + new_delay) >> 1;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + break;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + default: /* Performance, straight to maximum */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.max_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + break;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - /*<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - * For better performance, jump directly<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - * to RPe if we're below it.<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> if (IS_VALLEYVIEW(dev_priv->dev) &&<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay < dev_priv->rps.rpe_delay)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> new_delay = dev_priv->rps.rpe_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> } else<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> new_delay = dev_priv->rps.cur_delay - 1; @@ -743,13 +761,15 @@
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> static void gen6_pm_rps_work(struct work_struct *work)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> /* sysfs frequency interfaces may have snuck in while servicing the<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> * interrupt<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - if (new_delay >= dev_priv->rps.min_delay &&<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - new_delay <= dev_priv->rps.max_delay) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - if (IS_VALLEYVIEW(dev_priv->dev))<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - valleyview_set_rps(dev_priv->dev, new_delay);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - else<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - gen6_set_rps(dev_priv->dev, new_delay);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> - }<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + if (new_delay < dev_priv->rps.min_delay)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.min_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + if (new_delay > dev_priv->rps.max_delay)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + new_delay = dev_priv->rps.max_delay;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + if (IS_VALLEYVIEW(dev_priv->dev))<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + valleyview_set_rps(dev_priv->dev, new_delay);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + else<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + gen6_set_rps(dev_priv->dev, new_delay);<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> if (IS_VALLEYVIEW(dev_priv->dev)) {<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> /*<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> diff --git a/drivers/gpu/drm/i915/intel_pm.c
<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> b/drivers/gpu/drm/i915/intel_pm.c index 4e6d618..e9e467c 100644<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> --- a/drivers/gpu/drm/i915/intel_pm.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> +++ b/drivers/gpu/drm/i915/intel_pm.c<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> @@ -3242,6 +3242,7 @@ static void gen6_enable_rps(struct drm_device *dev)<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> /* In units of 50MHz */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> + dev_priv->rps.rp1_delay = (rp_state_cap & 0xff00) >> 8;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> dev_priv->rps.cur_delay = 0;<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> <o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">> /* disable the counters and set deterministic thresholds */<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">--<o:p></o:p></span></p>
<p class="MsoPlainText"><span lang="EN-US">Jesse Barnes, Intel Open Source Technology Center<o:p></o:p></span></p>
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