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<p class="MsoNormal">Patches looks fine. <o:p></o:p></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Californian FB","serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal">Reviewed-by: Deepak S <<span class="MsoHyperlink">deepak.s@inel.com</span><a href="mailto:jbarnes@virtuousgeek.org"></a>><span style="font-size:11.0pt;font-family:"Californian FB","serif";color:#1F497D"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Californian FB","serif";color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri","sans-serif""><o:p> </o:p></span></b></p>
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<p class="MsoNormal">From: <b>Jesse Barnes</b> <<a href="mailto:jbarnes@virtuousgeek.org">jbarnes@virtuousgeek.org</a>><br>
Date: Fri, Nov 15, 2013 at 11:02 PM<br>
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/vlv: use parallel context restore when coming out of RC6<br>
To: <a href="mailto:intel-gfx@lists.freedesktop.org">intel-gfx@lists.freedesktop.org</a><br>
<br>
<br>
Setting this bit restores all ring contexts in parallel rather than<br>
serially. Matches current BWG recommendations.<br>
<br>
Tested-by: "Meng, Mengmeng" <<a href="mailto:mengmeng.meng@intel.com">mengmeng.meng@intel.com</a>><br>
Signed-off-by: Jesse Barnes <<a href="mailto:jbarnes@virtuousgeek.org">jbarnes@virtuousgeek.org</a>><br>
---<br>
drivers/gpu/drm/i915/i915_reg.h | 1 +<br>
drivers/gpu/drm/i915/intel_pm.c | 2 +-<br>
2 files changed, 2 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h<br>
index 849e595..40b1136 100644<br>
--- a/drivers/gpu/drm/i915/i915_reg.h<br>
+++ b/drivers/gpu/drm/i915/i915_reg.h<br>
@@ -4891,6 +4891,7 @@<br>
#define GEN6_RC_CTL_RC6_ENABLE (1<<18)<br>
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)<br>
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)<br>
+#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)<br>
#define GEN7_RC_CTL_TO_MODE (1<<28)<br>
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)<br>
#define GEN6_RC_CTL_HW_ENABLE (1<<31)<br>
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c<br>
index 5d3912a..6a21d11 100644<br>
--- a/drivers/gpu/drm/i915/intel_pm.c<br>
+++ b/drivers/gpu/drm/i915/intel_pm.c<br>
@@ -4110,7 +4110,7 @@ static void valleyview_enable_rps(struct drm_device *dev)<br>
VLV_MEDIA_RC6_COUNT_EN |<br>
VLV_RENDER_RC6_COUNT_EN));<br>
if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)<br>
- rc6_mode = GEN7_RC_CTL_TO_MODE;<br>
+ rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;<br>
<br>
intel_print_rc6_info(dev, rc6_mode);<br>
<span style="color:#888888"><br>
<span class="hoenzb">--</span><br>
<span class="hoenzb">1.8.4.2</span><br>
<br>
<span class="hoenzb">_______________________________________________</span><br>
<span class="hoenzb">Intel-gfx mailing list</span><br>
<span class="hoenzb"><a href="mailto:Intel-gfx@lists.freedesktop.org">Intel-gfx@lists.freedesktop.org</a></span><br>
<span class="hoenzb"><a href="http://lists.freedesktop.org/mailman/listinfo/intel-gfx" target="_blank">http://lists.freedesktop.org/mailman/listinfo/intel-gfx</a></span></span><o:p></o:p></p>
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<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">-- <br>
Deepak S <o:p></o:p></p>
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