<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"> <html><head><title>DPR-120 CTS Test Report</title> <meta http-equiv="Content-Type" content="text/html; charset=Windows-1252"> <style> TABLE.DOCUMENT{width: 100%;} P.CONTENTS{font-weight: bold;font-family: "Arial";font-size: 11pt;margin-left: 0.3cm;margin-top: 10;margin-bottom: 0.3cm;color: #000000;} P.HEADING{background-color: #BBC3FF;margin-top: 0;margin-bottom: 0.5cm;margin-left: 0cm;font-weight: bold;font-family: "Arial";font-size: 16pt;color: #000000;} P.SUBHEADING{background-color: #BBC3FF;margin-top: 1.25cm;margin-bottom: 0.5cm;margin-left: 0.5cm;margin-right: 0;font-weight: bold;font-family: "Arial";font-size: 12pt;color: #000000;text-transform: uppercase;} P.GREENSUBHEADING{background-color: #DCFABC;margin-top: 0.5cm;margin-bottom: 0.5cm;margin-left: 0.6cm; margin-right: 0; font-weight: bold;font-family: "Arial";font-size: 12pt;color: #000000;} P.BODYTEXT{margin-top: 0;margin-bottom: 0;margin-left: 1.0cm;font-weight: medium;font-family: "Arial";font-size: 11pt;color: #000000;} P.BODYDETAILTEXT{margin-top: 0;margin-bottom: 0;margin-left: 1.4cm;font-weight: medium;font-family: "Arial";font-size: 9pt;color: #000000;} P.CONTENTS SELECT{font-weight: normal;font-family: "Arial";font-size: 11pt;width: 98%;margin-top: 0;text-align: left;} </style> <script type="text/javascript"> function Hide(iElementIndex) { document.getElementById("ID"+iElementIndex).style.display = 'none'; } function Show(iElementIndex) { document.getElementById("ID"+iElementIndex).style.display = 'inline'; } function HideAll(iDivCount) { for(var i=0;i<iDivCount;i++) { Hide(i); }} function ShowAll(iDivCount) { for(var i=0;i<iDivCount;i++) { Show(i); }} function ListHandler (iOptionValue) { if(iOptionValue==-1) { ShowAll(11); return; } HideAll(11); Show(iOptionValue); } </script> </head> <body onload='ListHandler(0);'> <div> Unigraf DPR-120 CTS Test Report</div> <div> <table class="DOCUMENT" cellpadding="0" cellspacing="0"> <colgroup> <col width="200"> <col width="*"> </colgroup> <td>Select item to display</td> <td><select id="testlist" onclick="ListHandler (document.getElementById ('testlist').value)" onkeyup="ListHandler (document.getElementById ('testlist').value)"> <option value="0">Report Summary</option> <option value="1">Test Summary</option> <option value="2">(400.3.1.1) </option> <option value="3">(400.3.1.2) </option> <option value="4">(400.3.1.3) </option> <option value="5">(400.3.1.4) </option> <option value="6">(400.3.1.5) </option> <option value="7">(400.3.1.6) </option> <option value="8">(400.3.1.7) </option> <option value="9">(400.3.1.8) </option> <option value="10">(loop count > 5):</option> <option value="-1">Show everything</option> </select> </td> </table> <div id="ID0"> Report summary DPR-120 Serial Number: 1350C367 Firmware Release Package: Firmware package Version 1.5 Detailed version data: [F1.3.0_N1.0.0_A1.0.0_V1.1.4] DPR-120 Debug and Test Controller version: 1.5.5 Report generated: 2:01, 15-4-2014 DUT Device/Model name: HW Revision: Serial number: Firmware version: Driver version: Testing conducted by: Remarks: Test results summary Total number of test runs: 9 Passed test runs: 2 Failed test runs: 7 Skipped test runs: 0 Aborted test runs: 0 </div> <div id="ID1"> Summary of individual test runs (400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension Test Result: PASSED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence Test Result: PASSED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. (400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence (loop count > 5): HBR2 Extension Test Result: FAILED Test settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. </div><div id="ID2"> Test Details, Test 1 (400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension Test Result: PASSED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.1) Successful LT at All Supported Lane Counts and Link Speeds: HBR2 Extension. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 1 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 81 Source DUT sets LANE_COUNT_SET = 1 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 21 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 1 lanes CR lock succeeded on all active lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 2&nbsp&nbsp 23 00 Source DUT writes TRAINING_PATTERN_SET = 23h _EQ LT iter_, 1 lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 01 00 80 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 1&nbsp&nbsp 08 _EQ LT iter_, 1 lanes Equalization succeeded on all active lanes Symbol lock succeeded on all active lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00 Source DUT writes TRAINING_PATTERN_SET = 0h Link training OK Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 44 44 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 07 00 81 00 44 44 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes CR lock succeeded on all active lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00 Source DUT writes TRAINING_PATTERN_SET = 23h _EQ LT iter_, 2 lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 08 08 _EQ LT iter_, 2 lanes Equalization succeeded on all active lanes Symbol lock succeeded on all active lanes All lanes are properly skewed &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00 Source DUT writes TRAINING_PATTERN_SET = 0h Link training OK Test PASSED </div><div id="ID3"> Test Details, Test 2 (400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.2) Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence: HBR2 Extension. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes Adjust request - voltage swing level 1 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 01 01 _CR LT iter_, 2 lanes Adjust request - voltage swing level 2 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 66 66 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 2A 2A TRAINING_LANE0_SET.MAX_SWING_REACHED = 0 TRAINING_LANE1_SET.MAX_SWING_REACHED = 0 _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _EQ LT iter_, 2 lanes Test FAILED, step 13, error 23: Maximum voltage swing is not reached </div><div id="ID4"> Test Details, Test 3 (400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.3) Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension. Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 0Ah &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes Adjust request - voltage swing level 1 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 01 01 _CR LT iter_, 2 lanes Adjust request - voltage swing level 2 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 66 66 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 2A 2A TRAINING_LANE0_SET.MAX_SWING_REACHED = 0 TRAINING_LANE1_SET.MAX_SWING_REACHED = 0 _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _EQ LT iter_, 2 lanes Test FAILED, step 13, error 23: Maximum voltage swing is not reached </div><div id="ID5"> Test Details, Test 4 (400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.4) Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension. Set MAX_LINK_RATE = 0Ah, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 0Ah &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 22 00 00 _EQ LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 81 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 0A 82 Source DUT sets LINK_BW_SET = 0Ah Expected LINK_BW_SET = 06h _CR LT iter_, 2 lanes _EQ LT iter_, 2 lanes _EQ LT iter_, 2 lanes Test FAILED, step 11, error 5: Link bandwidth does not match expected value </div><div id="ID6"> Test Details, Test 5 (400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence Test Result: PASSED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.5) Successful LT with Request of a Higher Pre-emphasis and Post Cursor 2 Setting During Channel Equalization Sequence. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes CR lock succeeded on all active lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00 Source DUT writes TRAINING_PATTERN_SET = 23h _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 08 08 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 CC CC &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes Equalization succeeded on all active lanes Symbol lock succeeded on all active lanes All lanes are properly skewed &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 CC CC &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 1&nbsp&nbsp 00 Source DUT writes TRAINING_PATTERN_SET = 0h Link training OK Test PASSED </div><div id="ID7"> Test Details, Test 6 (400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.6) Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence: HBR2 Extension. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 CC CC &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 CC CC Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes CR lock succeeded on all active lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00 Source DUT writes TRAINING_PATTERN_SET = 23h _EQ LT iter_, 2 lanes Clear LANEx_x_STATUS Wait until Source DUT terminates link training &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes _EQ LT iter_, 2 lanes Test FAILED, step 12, error 13: Invalid Training Pattern </div><div id="ID8"> Test Details, Test 7 (400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.7) Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing: HBR2 Extension. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes Adjust request - voltage swing level 1 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 11 11 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 01 01 _CR LT iter_, 2 lanes Adjust request - voltage swing level 2 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 66 66 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 2A 2A TRAINING_LANE0_SET.MAX_SWING_REACHED = 0 TRAINING_LANE1_SET.MAX_SWING_REACHED = 0 _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _CR LT iter_, 2 lanes _EQ LT iter_, 2 lanes Test FAILED, step 13, error 23: Maximum voltage swing is not reached </div><div id="ID9"> Test Details, Test 8 (400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.8) Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing: HBR2 Extension. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 00 00 _CR LT iter_, 2 lanes Adjust request - voltage swing level 0 Clear LANEx_x_STATUS &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 00 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00 Source DUT writes TRAINING_PATRN_SET = 23h _EQ LT iter_, 2 lanes Test FAILED, step 12, error 13: Invalid Training Pattern </div><div id="ID10"> Test Details, Test 9 (400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence (loop count > 5): HBR2 Extension Test Result: FAILED Test Settings: DUT Capabilities: Max Lanes = 2 Lanes, Max Link Rate = RBR (1.62 Gbps)HPD Unplug timeout: 700 ms Test automation: LLCTS_TEST_LINK_TRAINING LLCTS_TEST_PATTERN LLCTS_TEST_AUDIO_PATTERN LLCTS_TEST_TIMING LLCTS_TEST_STEREO_3D Event indicating DUT ready = Link Training end. Test Log Starting Test: (400.3.1.9) Unsuccessful LT due to Failure in Channel Equalization Sequence (loop count > 5): HBR2 Extension. Set MAX_LINK_RATE = 06h, MAX_LANE_COUNT = 2 Long HPD Pulse (700 ms) &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 77 00 81 00 00 00 Wait until Source DUT writes to the LINK_BW_SET and LANE_COUNT_SET fields &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 Source DUT sets LANE_COUNT_SET = 2 Source DUT sets LINK_BW_SET = 06h &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATTERN_SET = 21h _CR LT iter_, 2 lanes CR lock succeeded on all active lanes &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 00 80 00 00 00 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 23 00 00 Source DUT writes TRAINING_PATTERN_SET = 23h _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 80 00 44 44 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 08 08 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x103:&nbsp 2&nbsp&nbsp 30 30 _EQ LT iter_, 2 lanes Set LANEx_x_STATUS = 1111h &nbsp&nbsp AUX RD:&nbsp 0x202:&nbsp 6&nbsp&nbsp 11 11 81 00 88 88 &nbsp&nbsp AUX WR:&nbsp 0x100:&nbsp 2&nbsp&nbsp 06 82 &nbsp&nbsp AUX WR:&nbsp 0x102:&nbsp 3&nbsp&nbsp 21 00 00 Source DUT writes TRAINING_PATRN_SET = 21h _CR LT iter_, 2 lanes _EQ LT iter_, 2 lanes _EQ LT iter_, 2 lanes Test FAILED, step 23, error 13: Invalid Training Pattern </div> </div> <hr> Unigraf Oy | Piispantilankuja 4 | 02240 Espoo | Finland | +358-9-859 550 E-mail: <a href="mailto:info@unigraf.fi">info@unigraf.fi</a> | Web site: <a href="http://www.unigraf.fi">www.unigraf.fi</a> </body> </html>