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<p class="MsoNormal"><span lang="EN-US">Hi,<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US">I am developing the HSW’s OCL driver in the linux. I encounter a LRI problem on HSW.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US">Some gpgpu's applications, which use the shared local memory, must load the L3CTRLREG2 and L3CTRLREG3 registers to allocate the SLM in the L3 cache.
<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US">So I add L3CTRLREG2 and L3CTRLREG3 to the gen7_render_regs to pass the cmds parse when exec buffer. But it still don’t work.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US">I notice that, on HSW, the commands that load the register, such as MI_LOAD_REGISTER_IMM, will be converted to NOOP by the GPU if the batch buffer's MI_BATCH_NON_SECURE_HSW bit is set. And after
parse cmd, the MI_BATCH_NON_SECURE_HSW still set in the kernel. So HSW don’t accept LRI commands.<o:p></o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal" style="text-indent:21.0pt"><span lang="EN-US">Can I load these registers in the user space? Or should I hack the kernel?<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US">Yang Rong<o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US"><o:p> </o:p></span></p>
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